Analog circuits in ultra-deep-submicron CMOS
Anne-Johan Annema,Bram Nauta,R. van Langevelde,H. Tuinhout +3 more
- Vol. 40, Iss: 1, pp 132-143
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TLDR
In this paper, the gate-leakage mismatch exceeds conventional matching tolerances, and the drop in supply voltages can solve this problem by exploiting combinations of thin and thick-oxide transistors.Abstract:
Modern and future ultra-deep-submicron (UDSM) technologies introduce several new problems in analog design. Nonlinear output conductance in combination with reduced voltage gain pose limits in linearity of (feedback) circuits. Gate-leakage mismatch exceeds conventional matching tolerances. Increasing area does not improve matching any more, except if higher power consumption is accepted or if active cancellation techniques are used. Another issue is the drop in supply voltages. Operating critical parts at higher supply voltages by exploiting combinations of thin- and thick-oxide transistors can solve this problem. Composite transistors are presented to solve this problem in a practical way. Practical rules of thumb based on measurements are derived for the above phenomena.read more
Citations
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Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations
Ben Varkey Benjamin,Peiran Gao,Emmett McQuinn,Swadesh Choudhary,Anand R. Chandrasekaran,Jean-Marie Bussat,Rodrigo Alvarez-Icaza,John V. Arthur,Paul A. Merolla,Kwabena Boahen +9 more
TL;DR: Neurogrid as discussed by the authors is a real-time neuromorphic system for simulating large-scale neural models in real time using 16 Neurocores, including axonal arbor, synapse, dendritic tree, and soma.
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A/D converter trends: Power dissipation, scaling and digitally assisted architectures
TL;DR: This paper summarizes recent trends in the area of low-power A/D conversion and a discussion on minimalistic and digitally assisted design approaches is used to sketch a route toward further improvements in ADC power efficiency and performance.
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Analog Circuit Design in Nanoscale CMOS Technologies
TL;DR: A survey of the evolution of figure of merit for analog-to-digital converters and factors affecting device matching, including those relating to single devices as well as local and long-distance matching effects are presented.
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A Comparator With Reduced Delay Time in 65-nm CMOS for Supply Voltages Down to 0.65 V
Bernhard Goll,Horst Zimmermann +1 more
TL;DR: A comparator in a low-power 65-nm complementary metal-oxide-semiconductor process (only standard transistors with threshold voltage Vt ap 0.4 V were used) is presented, where the circuit of a conventional latch-type comparator consisting of two cross-coupled inverters is modified for fast operation, even with 0.65-V supply.
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Power Dissipation Bounds for High-Speed Nyquist Analog-to-Digital Converters
TL;DR: An attempt to estimate a lower bound for the power of ADCs, based on first principles and using pipeline and flash architectures as examples, finds that power dissipation of high-resolution ADCs is bound by noise, whereas technology is the limiting factor for low-resolution devices.
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