Patent
CMOS semiconductor device and method of fabricating the same
TLDR
In this paper, a complementary metal-oxide semiconductor (CMOS) device and a method of fabricating the CMOS semiconductor device are described. But the method is not described.Abstract:
Example embodiments provide a complementary metal-oxide semiconductor (CMOS) semiconductor device and a method of fabricating the CMOS semiconductor device. The CMOS semiconductor device may include gates in the nMOS and pMOS areas, polycrystalline silicon (poly-Si) capping layers, metal nitride layers underneath the poly-Si capping layers, and a gate insulating layer underneath the gate. The metal nitride layers of the nMOS and pMOS areas may be formed of the same type of material and may have different work functions. Since a metal gate is formed of identical types of metal nitride layers, a process may be simplified, yield may be increased, and a higher-performance CMOS semiconductor device may be obtained.read more
Citations
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Semiconductor device, and manufacturing method thereof
TL;DR: In this article, the oxide semiconductor film has at least a crystallized region in a channel region, which is defined as a region of interest (ROI) for a semiconductor device.
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Semiconductor devices and methods of fabricating the same
TL;DR: In this paper, a semiconductor device includes capacitors connected in parallel, and a capacitor-dielectric layer is disposed between each of the capping electrodes and each of electrode active portions that overlap each other.
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Integrated circuit device and method of manufacturing the same
TL;DR: In this article, the authors proposed a method for providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of the active regions, where each of the first gate line and second gate line crossing at least one active region.
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Semiconductor device and fabricating method thereof
TL;DR: In this paper, a semiconductor device with a first fin on a substrate, a first gate electrode formed on the substrate to intersect the first fin, and a first elevated source/drain on both sides of the first gate electrodes was provided.
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Semiconductor Device and Method for Fabricating the Same
TL;DR: In this article, a gate spacer is formed on a sidewall of the recess gate and an insulating film is selectively etched to form a landing plug contact hole, which is then filled with a conductive layer.
References
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Patent
Method of manufacturing a transistor in a semiconductor device
TL;DR: In this paper, a method of manufacturing a transistor in a semiconductor device was disclosed, which can lower the threshold voltage by implementing a surface channel CMOS device both in the NMOS region and the PMOS region.
Patent
ULSI MOS with high dielectric constant gate insulator
TL;DR: In this paper, a MOS transistor formed on a semiconductor substrate of a first conductivity type and method of fabrication are provided, which includes an interfacial layer formed on the substrate, a high dielectric constant layer covering the interfacial layers, and a gate electrode having a width of less than 0.3 micron.
Patent
Temperature stable metal nitride gate electrode
TL;DR: In this paper, an integrated circuit is provided including an FET gate structure formed on a substrate, which includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate and in contact therewith.
Patent
Transistor devices, CMOS constructions, capacitor constructions, and methods of forming transistor devices and capacitor constructions
TL;DR: In this article, a metal-containing material comprising a thickness of no more than 20 A (or alternatively, a thickness resulting from a number of ALD cycles) is formed between conductively-doped silicon and a dielectric layer.
Patent
Method for forming dual gate of semiconductor device
TL;DR: In this paper, a method for manufacturing a dual gate of a semiconductor device is provided to make a gate electrode completely doped without boron penetration by implanting B11 ions into an amorphous silicon layer so that a p-gate is formed, and to form a source/drain region of a shallow junction by making BF2 ions not implanted into the p gate because of an O3 tetraethoxysilane(TEOS) oxide layer of 500 angstrom.