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Congestion and Power Integrity Aware Placement and Routing for 3D Packaging

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TLDR
This work integrates noise analysis and decap estimation in the floorplanning process and uses the global routers results directly to estimate congestion and tight couple global routing with floorplaning to get a better area/congestion tradeoff.
Abstract
One of the major concerns for a 3-D package is to deal with power supply noise. Decoupling Capacitances (decap) allocation is a powerful technique to suppress power supply noise. In this work we integrate noise analysis and decap estimation in the floorplanning process. We also use the global routers results directly to estimate congestion and tight couple global routing with floorplanning to get a better area/congestion tradeoff. Our experiments prove the quality of our approach. We obtain improvements in both decap amount and congestion with only small increase in area, wirelength and runtime.

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Proceedings ArticleDOI

B*-Trees: a new representation for non-slicing floorplans

TL;DR: An efficient, flexible, and effective data structure, B-trees for non-slicing floorplans, based on ordered binary trees and the admissible placement presented in [1], and a B-tree based simulated annealing scheme for floorplan design.
Proceedings ArticleDOI

Rectangle-packing-based module placement

TL;DR: A P-admissible solution space where each packing is represented by a pair of module name sequences is proposed, and hundreds of modules could be successfully packed as demonstrated.
Proceedings ArticleDOI

An O-tree representation of non-slicing floorplan and its applications

TL;DR: A deterministic floorplanning algorithm utilizing the structure of O-tree is developed with promising performance with average 16% improvement in wire length, and 1% less in dead space over previous CPU-intensive cluster refinement method.
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