Proceedings ArticleDOI
Consistency Check through O-GEHL Predictors
Ehsan Atoofian
- pp 218-224
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TLDR
This paper introduces Adaptive Clock (AC), a speculative approach which dynamically selects one of the two validation techniques based on probability of conflicts which is effective and improves performance of transactional applications up to 33%.Abstract:
Transactional Memory (TM) is a promising paradigm to facilitate parallel programming for multicore processors. In Software implementation of TMs (STMs), transactions rely on a global clock to maintain consistency of transactional data. While this method is simple to implement, it results in significant timing overhead if transactions commit frequently. The alternative approach is Thread Local Clock (TLC) which exploits decentralized local variables to maintain consistency in transactions. However, TLC may increase false aborts and degrade performance of STMs. In this paper, we introduce Adaptive Clock (AC) which dynamically selects one of the two validation techniques based on probability of conflicts. AC is a speculative approach and relies on O-GEHL predictors to speculate future conflicts. We have incorporated AC into TL2 and compared the performance of the new implementation with the original STM using Stamp v0.9.10 benchmark suite. Our results reveal that AC is effective and improves performance of transactional applications up to 33%.read more
Citations
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Journal ArticleDOI
Boosting performance of transactional memory through O-GEHL predictors
TL;DR: This paper analyzes global clock and TLC in the context of STM systems, highlighting both the implementation trade-offs and the performance implications of the two techniques and concludes that neither global clock nor TLC is optimum across applications.
Proceedings ArticleDOI
Read-Write Lock Allocation in Software Transactional Memory
TL;DR: This paper introduces two optimization techniques to overcome the overhead of the global clock - Read-Write Lock Allocation (RWLA) and an adaptive technique which dynamically selects either baseline scheme or RWLA.
Proceedings ArticleDOI
Acceleration of Software Transactional Memory through Hardware Clock
TL;DR: The hardware clock is implemented on the processor chip and enables bottleneck-free transactional memory run-time systems and reduces execution time of Stamp benchmarks up to 62%.
References
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Proceedings ArticleDOI
Software transactional memory
Nir N. Shavit,Dan Touitou +1 more
TL;DR: STM is used to provide a general highly concurrent method for translating sequential object implementations to non-blocking ones based on implementing a k-word compare&swap STM-transaction, a novel software method for supporting flexible transactional programming of synchronization operations.
Proceedings ArticleDOI
Software transactional memory for dynamic-sized data structures
TL;DR: A new form of software transactional memory designed to support dynamic-sized data structures, and a novel non-blocking implementation of this STM that uses modular contention managers to ensure progress in practice.
Journal Article
Transactional locking II
Dave Dice,Ori Shalev,Nir Shavit +2 more
TL;DR: This paper introduces the transactional locking II (TL2) algorithm, a software transactional memory (STM) algorithm based on a combination of commit-time locking and a novel global version-clock based validation technique, which is ten-fold faster than a single lock.
Book ChapterDOI
Transactional locking II
Dave Dice,Ori Shalev,Nir Shavit +2 more
TL;DR: TL2 as mentioned in this paper is a software transactional memory (STM) algorithm based on a combination of commit-time locking and a novel global version-clock based validation technique, which is ten times faster than a single lock.
Journal ArticleDOI
Language support for lightweight transactions
Tim Harris,Keir Fraser +1 more
TL;DR: It is argued that these problems can be addressed by moving to a declarative style of concurrency control in which programmers directly indicate the safety properties that they require, which is easier for mainstream programmers to use, prevents lock-based priority-inversion and deadlock problems and can offer performance advantages.