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Proceedings ArticleDOI

Data processing boards design for CBM experiment

TLDR
The evolution of the concepts leading from the functional requirements of the control and readout systems of the CBM experiment to the design of prototype implementation of the DPB boards are described and requirements on the board level and on the crate level are described.
Abstract
This paper presents a concept of the Data Processing Boards for the Compressed Baryonic Matter (CBM) experiment. Described is the evolution of the concepts leading from the functional requirements of the control and readout systems of the CBM experiment to the design of prototype implementation of the DPB boards. The paper describes requirements on the board level and on the crate level. Finally it discusses the prototype design prepared for testing and verification of proposed solutions, and selection of the final implementation.

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Citations
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Proceedings ArticleDOI

Time and clock synchronization with AFCK for CBM

TL;DR: The AMC FMC Carrier Kintex (AFCK) board is a prototype of Data Processing Board (DPB) for CBM experiment and function will be described, which will serve as a data hub and communication interconnection.
Proceedings ArticleDOI

Selection of hardware platform for CBM Common Readout Interface

TL;DR: The paper presents the analysis performed to select the optimal hardware platform for the CBM CRI, considering the cost and the number of input links serviced by a single board.
Proceedings ArticleDOI

The GBT-based readout concept for the silicon tracking system of the CBM experiment

TL;DR: In this paper, the authors present the readout concept for the Silicon Tracking System (STS) of the CBM experiment at FAIR, which is designed to handle interaction rates up to 10 MHz with hundreds of tracks in fixed target heavy ion collisions of up to 35 AGeV.
Proceedings ArticleDOI

CRI board for CBM experiment: preliminary studies

TL;DR: The preliminary analysis and experiments performed to assess the possibility to implement the CRI firmware in the selected prototyping hardware platform and functionalities provided by the Zynq UltraScale+ platform regarding their usability for the creation of the PCIe-based data concentration system are presented.
Journal ArticleDOI

Design of versatile ASIC and protocol tester for CBM readout system

TL;DR: The paper describes the FPGA-based tester platform which can be used both for the verification of the protocol implementation in a front-end ASIC at the design stage, and for testing of the produced ASICs.
References
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BookDOI

The CBM Physics Book

TL;DR: The CBM Experiment as discussed by the authors has been used to study the properties of Strongly Interacting Matter (SIM) and its effects on collision dynamics and the CBM experiment in the real world.

The GBT Project

TL;DR: The GigaBit Transceiver (GBT) architecture and transmission protocol has been proposed for data transmission in the physics experiments of the future upgrade of the LHC accelerator, the SLHC as discussed by the authors.
Journal ArticleDOI

The GBT-SerDes ASIC prototype

TL;DR: The GBT-SerDes architecture is described, the test results are presented, and the transceiver serializes-deserializes the data, Reed- Solomon encodes and decodes the data and scrambles and descrambles the data for transmission over optical fibre links.
Journal ArticleDOI

The CBM time-of-flight wall

TL;DR: In this article, the authors proposed two extreme regions: an outermost region (low rate/low multiplicity) covered by float glass RPCs in multi-strip fashion, and a central region (high rate/high multiplicity), consisting of densely packed readout cells made with low resistive electrodes.

Implementing the GBT data transmission protocol in FPGAs

TL;DR: This paper describes efficient physical implementation of the GBT protocol achieved for FPGA devices on Altera and Xilinx devices with source codes developed in Verilog and VHDL with the only aim to demonstrate the ability of both AlterA andXilinx FPGAs to host such a protocol with excellent performances.