Journal ArticleDOI
Design Considerations for Single-Chip Computers of the Future
Patterson,Sequin +1 more
TLDR
It is concluded that a viable modular building block for the next generation of computing systems will be a self-contained computer on a single chip.Abstract:
In the mid 1980's it will be possible to put a million devices (transistors or active MOS gate electrodes) onto a single silicon chip. General trends in the evolution of silicon integrated circuits are reviewed and design constraints for emerging VLSI circuits are analyzed. Desirable architectural features in modern computers are then discussed and consequences for an implementation with large-scale integrated circuits are investigated. The resulting recommended processor design includes features such as an on-chip memory hierarchy, multiple homogeneous caches for enhanced execution parallelism, support for complex data structures and high-level languages, a flexible instruction set, and communication hardware. It is concluded that a viable modular building block for the next generation of computing systems will be a self-contained computer on a single chip. A tentative allocation of the one milion transistors to the various functional blocks is given, and the result is a memory intensive design.read more
Citations
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Journal ArticleDOI
Low-power CMOS digital design
TL;DR: In this paper, techniques for low power operation are presented which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations to reduce power consumption in CMOS digital circuits while maintaining computational throughput.
Journal ArticleDOI
Digital signal processing for sonar
TL;DR: This paper is a tutorial which describes "main stream" sonar digital signal processing functions along with the associated implementation considerations to promote further cross-fertilization of ideas amongdigital signal processing applications in sonar, radar, speech, communications, seismology, and other related fields.
Journal ArticleDOI
Trace-driven memory simulation: a survey
Richard Uhlig,Trevor Mudge +1 more
TL;DR: A survey and analysis of trace-driven memory simulation tools can be found in this article, where the authors discuss the strengths and weaknesses of different approaches and show that no single method is best when all criteria, including accuracy, speed, memory, flexibility, portability, expense, and ease of use are considered.
Journal ArticleDOI
Communication Structures for Large Networks of Microcomputers
TL;DR: This paper compares nine network interconnection schemes and introduces "dual-bus hypercubes," a cost-effective method of connecting thousands of dual-port single-chip microcomputers into a room-sized information processing system, a "network computer."
Journal ArticleDOI
Concurrent VLSI Architectures
TL;DR: This tutorial paper addresses some of the principles and provides examples of concurrent architectures and designs that have been inspired by VLSI technology.
References
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Design of ion-implanted MOSFET's with very small physical dimensions
TL;DR: This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/.
Journal ArticleDOI
The CRAY-1 computer system
TL;DR: The CRAY-1 is the only computer to have been built to date that satisfies ERDA's Class VI requirement (a computer capable of processing from 20 to 60 million floating point operations per second) and its Fortran compiler (CFT) is designed to give the scientific user immediate access to the benefits of the Cray-1's vector processing architecture.
Proceedings ArticleDOI
X-Tree: A tree structured multi-processor computer architecture
TL;DR: The problem of organizing multiple, monolithic microprocessors into an effective general purpose computer structure is examined and a tree structure with extra interconnections was found to be especially attractive.
Book
Microprogramming: principles and practices
Samir S. Husson,Paula Schneider +1 more
TL;DR: Details how one can use a four-state cell to store logic which has been ex'and-not' and 'exclusive-or' functions as well as the standard sum of products to recognize these additional functions further reduces the size of required memory.