Proceedings ArticleDOI
Design of Networks-on-Chip for Real-Time Multi-processor Systems-on-Chip
Jens Sparsø
- pp 1-5
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TLDR
The aim of this project is to develop a general-purpose multi-core platform for real-time systems as well as tools supporting its use (compiler, simulator, and worst-case execution time analysis tool).Abstract:
This paper addresses the design of networks-on-chips for use in multi-processor systems-on-chips - the hardware platforms used in embedded systems. These platforms typically have to guarantee real-time properties, and as the network is a shared resource, it has to provide service guarantees (bandwidth and/or latency) to different communication flows. The paper reviews some past work in this field and the lessons learned, and the paper discusses ongoing research conducted as part of the project "Time-predictable Multi-Core Architecture for Embedded Systems" (T-CREST), supported by the European Commissions seventh framework programme. The aim of this project is to develop a general-purpose multi-core platform for real-time systems as well as tools supporting its use (compiler, simulator, and worst-case execution time analysis tool).read more
Citations
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Journal ArticleDOI
Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation
Evangelia Kasapaki,Martin Schoeberl,Rasmus Bo Sørensen,Christoph Thomas Muller,Kees Goossens,Jens Sparsø +5 more
TL;DR: An area-efficient, globally asynchronous, locally synchronous network-on-chip (NoC) architecture for a hard real-time multiprocessor platform that uses statically scheduled time-division multiplexing (TDM) to control the communication over a structure of routers, links, and network interfaces (NIs).
Journal ArticleDOI
Survey on Real-Time Networks-on-Chip
TL;DR: The challenges faced, when designing NoCs for real-time applications are discussed and contributions in this area are surveyed on the level of guaranteed Quality-of-Service support, adaptivity, and energy efficient techniques.
Proceedings ArticleDOI
Argo: A Time-Elastic Time-Division-Multiplexed NOC Using Asynchronous Routers
Evangelia Kasapaki,Jens Sparsø +1 more
TL;DR: This paper uses asynchronous routers in a time-division-multiplexed network-on-chip (NOC), Argo, that is being developed for a multi-processor platform for hard real-time systems to achieve a simpler, smaller and more robust, self-timed design.
Proceedings ArticleDOI
A Metaheuristic Scheduler for Time Division Multiplexed Networks-on-Chip
TL;DR: A metaheuristic scheduler for inter-processor communication in multi-processor platforms using time division multiplexed (TDM) networks on chip (NOC) networks, which handles a broader and more general class of platforms.
Proceedings ArticleDOI
Parallel many-core avionics systems
Milos Panic,Eduardo Quinones,Pavel Zaykov,Carles Hernandez,Jaume Abella,Francisco J. Cazorla +5 more
TL;DR: In this article, the authors extend the concept of SWP by introducing parallel software partitions (pSWP) specification that describes the behavior of SWPs required when running in a many-core to enable incremental qualification.
References
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Journal ArticleDOI
AEthereal network on chip: concepts, architectures, and implementations
TL;DR: The AEthereal NoC is introduced, which provides guaranteed services (GSs) - such as uncorrupted, lossless, ordered data delivery; guaranteed throughput; and bounded latency - are essential for the efficient construction of robust SoCs and exploits the NoC capacity unused by the GS traffic.
Proceedings ArticleDOI
A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip
Tobias Bjerregaard,Jens Sparsø +1 more
TL;DR: This paper proposes a network-on-chip (NoC) router architecture that is based on clockless circuit techniques, and thus inherently supports a modular GALS-oriented design flow, and demonstrates with a CMOS standard cell design.
Proceedings ArticleDOI
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Proceedings ArticleDOI
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D. Wiklund,Dake Liu +1 more
TL;DR: The SoCBUS is explained together with the working principles of the transaction handling, and the concept of packet connected circuit, PCC, where a packet is switched through the network locking the circuit as it goes, is introduced.
Proceedings ArticleDOI
The Nostrum backbone-a communication protocol stack for Networks on Chip
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