Patent
Double-sided segmented line architecture in 3d integration
TLDR
In this article, a double-sided three-dimensional (3D) hierarchal architecture for multiple semiconductor wafers using an arrangement of through silicon vias (TSVs) and backside wiring is presented.Abstract:
Embodiments of the present invention relate generally to electronic components such as semiconductor wafers and more particularly, to a double-sided three-dimensional (3D) hierarchal architecture scheme for multiple semiconductor wafers using an arrangement of through silicon vias (TSVs) and backside wiring. In an embodiment a first word line architecture may be formed on a front side of an IC chip and connected to a second word line architecture formed on a back side of the IC chip through intra-wafer, TSVs, thereby relocating required wiring to the back side of the IC chip.read more
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Patent
3D semiconductor device and structure
TL;DR: In this article, an Integrated Circuit device including a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single-crystal transistors, where the second-layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of transistors that cross the first-dice lane.
Patent
Integrated circuit chip with power delivery network on the backside of the chip
Eric Beyne,Julien Ryckaert +1 more
TL;DR: In this article, an integrated circuit (IC) chip having power and ground rails incorporated in the front end of line (FEOL) is disclosed, where the connection from the buried interconnects to the source and drain areas is established by local interconnect.
Patent
Wafer three-dimensional integrated lead wire process for three-dimensional memory and structure thereof
TL;DR: In this article, a wafer three-dimensional integrated lead wire process and a structure of the process can be applied to wafer 3D integration process for the wafers of a 3D memory.
Patent
Power distribution for active-on-active die stack with reduced resistance
TL;DR: In this article, active-on-active microelectronic devices are described, where a first die is on a second die with a bottom surface of a first substrate facing a top surface of the second substrate, respectively, to provide a die stack.
Patent
Backside lookup table-based processor
TL;DR: A backside lookup table (BS-LUT)-based emulation processor for emulating a system is described in this paper. But the implementation of the system is limited to a single processor.
References
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Patent
Semiconductor device and structure
Zvi Or-Bach,Brian Cronquist +1 more
TL;DR: In this paper, a first layer and a second layer of layer-transferred mono-crystallized silicon, where the first layer comprises a first plurality of horizontally-oriented transistors, and the second layer includes a second plurality of vertically oriented transistors.
Patent
Integrated circuit chip using top post-passivation technology and bottom structure technology
TL;DR: In this article, the authors describe an over-passivation scheme at the top of the integrated circuit chip and a bottom scheme at a bottom of the IC using a top postpassivation technology and bottom structure technology.
Patent
Physically alternating sense amplifier activation
TL;DR: In this article, a memory device having banks of sense amplifiers comprising two types of senses amplifiers is described, where a first driver used to activate the first sense amplifier is embedded into a first bank, and a second driver used by the second sense amplifier to activate a second type of senses amplifier is inserted into a second bank.
Patent
Multiple class memory systems
TL;DR: In this article, a physical memory sub-system consisting of a first memory and a second memory is described, with the second memory being communicatively coupled to the first memory.
Patent
Through hole vias at saw streets including protrusions or recesses for interconnection
TL;DR: In this article, a contact pad is formed over and electrically connected to an active surface of the semiconductor die, and a gap is formed between the gap and an insulating material is deposited in the gap.