Electronic System-Level Synthesis Methodologies
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Citations
基于事务数据流的可重构SoC性能分析方法研究与实现 Research and Implementation of Reconfigurable SoC Transaction Level Architectural Performance Analysis Based on Transaction Data Stream
Scalable Design Space Exploration via Answer Set Programming
Evaluating synthesis tools for hardware implementation on ZYBO board
Dataflow Models of Computation for Programming Heterogeneous Multicores
References
The Semantics of a Simple Language for Parallel Programming.
Synchronous data flow
System Design with SystemC
A framework for comparing models of computation
Related Papers (5)
Frequently Asked Questions (14)
Q2. What are the future works mentioned in the paper "Electronic system-level synthesis methodologies" ?
Nevertheless, no single approach currently provides a complete solution, and further research in many areas is required. In the future, the authors plan to investigate such interoperability issues using combinations of different tools presented in this paper. On the other hand, based on the common concepts and principles identified in this classification, it should be possible to define interfaces such that different point tools can be combined into an overall ESL design environment. Last, but not least, the authors would like to thank the reviewers for their helpful comments and suggestions in making this paper a much stronger contribution.
Q3. What can be used to test values of internal variables and data in the input channels?
constant methods called guards (e.g., check) can be used to test values of internal variables and data in the input channels.
Q4. What is the process of finding a good architecture mapping?
Finding a good application-to-architecture mapping is carried out during a two-phase automatic architecture exploration step consisting of static and dynamic (i.e., simulative) exploration methods using a TAPM MoP.
Q5. How long did the prototyping work take?
Due to the highly automated design flow of Daedalus, all DSE and prototyping work was performed in only a short amount of time, five days in total.
Q6. What are examples of performance models for different classes of granularity?
Examples of simulation-based MoPs for different classes of timing granularity are cycle-accurate performance models (CAPMs), instruction-set-accurate performance models (ISAPMs), or task-accurate performance models (TAPMs) [12].
Q7. How can lower level flows be supplied?
Lower level flows can be supplied either in the form of corresponding synthesis tools or by providing predesigned intellectual property (IP) components to be plugged into the system architecture.
Q8. What is the FSM controlling the communication behavior of the SysteMoC actor?
The FSM controlling the communication behavior of the SysteMoC actor checks for available input data (e.g., #i1 ≥ 1) and available space on the output channels (e.g., #o1 ≥ 1) to store results.
Q9. What is the main observation that can be made from Fig. 1?
An important observation that can be made from Fig. 1 is that, at the RT level, hardware and software worlds unite again, both feeding into (traditional) logic design processes down to the final manufacturing output.
Q10. Why are many streaming applications not modeled as static dataflow graphs?
Due to the complexity of many streaming applications, they often cannot be modeled as static dataflow graphs [30], [31], where consumption and production rates are known at compile time.
Q11. How many lines of code is refined in the final TLM?
The complete cellphone specification consists of about 16 000 lines of SpecC code and is refined down to 30 000 lines in the final TLM.
Q12. What are the components of a Daedalus MPSoC?
These components include a variety of programmable processors, dedicated hardwired IP cores, memories, and interconnects, thereby allowing the implementation of a wide range of heterogeneous MPSoC platforms.
Q13. What is the simplest way to perform a concurrent KPN?
KPNgen [23] allows for automatically converting a sequential (SANLP) behavioral specification written in C into a concurrent KPN [22] specification.
Q14. What is the last step of the proposed ESL design flow?
Once this selection has been made, the last step of the proposed ESL design flow is the rapid prototyping of the corresponding FPGA-based implementation in terms of model refinement.