Proceedings ArticleDOI
Exploiting signal flow and logic dependency in standard cell placement
Jason Cong,Dongmin Xu +1 more
- pp 63
TLDR
This paper exploits the use of signal flow and logic dependency in standard cell placement by using the maximum fanout-free cone (MFFC) decomposition technique, and develops a containment tree based algorithm for splitting large MFFCs into smaller ones to get clusters with restricted sizes.Abstract:
Most existing placement algorithms consider only connectivity information during the placement process, and ignore other information available from the higher levels of design process. In this paper, we exploit the use of signal flow and logic dependency in standard cell placement by using the maximum fanout-free cone (MFFC) decomposition technique. We developed a containment tree based algorithm for splitting large MFFCs into smaller ones to get clusters with restricted sizes. We also developed a placement algorithm, named MFFC-TW, which first clusters the circuit based on MFFC decomposition and then feeds the clustered circuit to the Timberwolf 6.0 placement package. Very promising experimental results were obtained.read more
Citations
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Proceedings ArticleDOI
Large scale circuit partitioning with loose/stable net removal and signal flow based clustering
TL;DR: This paper presents an efficient Iterative Improvement based Partitioning (IIP) algorithm that combines signal flow based Maximum Fanout Free Subgraph (MFFS) clustering algorithm with Loose and Stable net Removal (LSR) partitioning algorithm, that outperforms the recent state-of-the-art IIP algorithms.
Patent
Digital circuit layout techniques
TL;DR: In this paper, a technique for analyzing digital circuits to identify pin swaps is provided for circuit layout and similar tasks in which the circuit is first decomposed into fanout-free regions.
Proceedings ArticleDOI
Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy
TL;DR: A performance-driven soft-macro clustering and placement method which preserves HDL design hierarchy to guide the soft- Macro placement process and a complete chip design methodology is presented by integrating the proposed method and a set of commercial EDA tools.
Proceedings ArticleDOI
Using partitioning to help convergence in the standard-cell design automation methodology
Hema Kapadia,Mark Horowitz +1 more
TL;DR: A standard-cell design methodology based on netlist partitioning as a solution for the problem of lack of convergence in the conventional methodology in deep submicron technologies and high correlation between synthesis estimates and post-placement measurements of wire-loads and gate delays is explored.
Patent
Using budgeted required time during technology mapping
TL;DR: In this paper, a method for selecting which covers to retain for each node reduces the computational burden for large logic cones and large cell libraries, where at each node only K covers are retained, and these covers have timing performances which are centered around the ideal timing performance for that node.
References
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Journal ArticleDOI
Fast spectral methods for ratio cut partitioning and clustering
L. Hagen,Andrew B. Kahng +1 more
TL;DR: It is shown that the second smallest eigenvalue of a matrix derived from the netlist gives a provably good approximation of the optimal ratio cut partition cost.
Book
Combinatorial Algorithms for Integrated Circuit Layout
TL;DR: This paper will concern you to try reading combinatorial algorithms for integrated circuit layout as one of the reading material to finish quickly.
Journal ArticleDOI
GORDIAN: VLSI placement by quadratic programming and slicing optimization
TL;DR: The authors present a placement method for cell-based layout styles that is composed of alternating and interacting global optimization and partitioning steps that are followed by an optimization of the area utilization.
Journal ArticleDOI
An r-Dimensional Quadratic Placement Algorithm
TL;DR: In this paper, the problem of placing n connected points (or nodes) in r-dimensional Euclidean space is given, and the criterion for optimality is minimizing a weighted sum of squared distances between the points subject to quadratic constraints of the form X′X = 1, for each of the r unknown coordinate vectors.
Journal ArticleDOI
Multiple-way network partitioning
TL;DR: A multiple-block network partitions algorithm adapted from a two-block iterative improvement partitioning algorithm and of the level gain concept to multiple blocks seeks to improve the partition uniformly with respect to all blocks as oppose to making repeated uses of two-way partitioning.