IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 35, NO. 2, MARCH/APRIL 1999 477
Fast-Clamped Short-Circuit Protection of IGBT’s
Vinod John, Student Member, IEEE, Bum-Seok Suh, and Thomas A. Lipo,
Fellow, IEEE
Abstract—Identification of fault current during the operation of
a power semiconductor switch and activation of suitable remedial
actions are important for reliable operation of power converters.
A short circuit is a basic and severe fault situation in a circuit
structure, such as voltage-source converters. This paper presents
a new active protection circuit for fast and precise clamping
and safe shutdown of fault currents of the insulated gate bipolar
transistors (IGBT’s). This circuit allows operation of the IGBT’s
with a higher on-state gate voltage, which can thereby reduce the
conduction loss in the device without compromising the short-
circuit protection characteristics. The operation of the circuit
is studied under various conditions, considering variation of
temperature, rising rate of fault current, gate voltage value, and
protection circuit parameters. An evaluation of the operation of
the circuit is made using IGBT’s from different manufacturers
to confirm the effectiveness of the protection circuit.
Index Terms—Fault current, fault under load, hard-switched
fault, insulated gate bipolar transistors, protection, short circuit.
I. INTRODUCTION
S
HORT CIRCUIT and overcurrent are severe fault con-
ditions that can result in failure of the insulated gate
bipolar transistor (IGBT) if appropriate remedial action is not
taken within a short time of the order of a few microseconds.
It is shown in [1] that the internal failure mechanism in
IGBT’s during short circuit is different from the case of hard-
switching inductive turn-off failure. Short circuit results in
local heating closer to the gate oxide in the IGBT and can
severely degrade the device. The excessive power dissipation
in the IGBT during the fault leads to chip heating, which
eventually destroys the device. Several methods for protection
of the IGBT are available that are used in intelligent power
modules and advanced gate driver chips [2]–[4]. However,
there are no benchmarks for the performance of these circuits.
Various approaches to protect IGBT’s have been proposed
and studied in [5]–[12]. Different topologies for fault-current-
limiting circuits (FCLC’s) have been investigated in [5] and
[6]. The technique used in [5], which utilizes a capacitor to
reduce the gate voltage after the fault, has the limitation that
the device current may shut off and be turned back on again,
Paper IPCSD 98–73, presented at the 1998 IEEE Applied Power Electronics
Conference and Exposition, Anaheim, CA, February 15–19, and approved
for publication in the IEEE T
RANSACTIONS ON INDUSTRY APPLICATIONS by
the Industrial Power Converter Committee of the IEEE Industry Applications
Society. Manuscript released for publication October 27, 1998.
V. John and T. A. Lipo are with the Department of Electrical and Computer
Engineering, University of Wisconsin, Madison, WI 53706 USA.
B.-S. Suh was with the Department of Electrical and Computer Engineering,
University of Wisconsin, Madison, WI 53706 USA. He is now with the
IGBT/MOSFET Group, Discrete Team, Samsung Electronics, Puchon-City,
Kyonggi Province, 420-711 Korea.
Publisher Item Identifier S 0093-9994(99)02239-2.
depending on the initial condition of the capacitor and its
value. Also, a large value of capacitance is necessary to prevent
the capacitor voltage from drifting back to the normal on-state
gate voltage. Multiple stages of clamping are proposed in [5]
to increase the endurance time and reduce the turn-off current
level. A pure zener-based clamp has the drawback that the
clamping gate voltage can be much larger under the transient
conditions of the fault. Reference [6] discusses a topology
where the zener and capacitive method is used to limit fault
currents. This circuit is effective in eventually clamping the
fault current level, but does not limit the large peak current that
flows immediately after the fault due to delay in its operation.
References [7]–[12] discuss methods to softly turn off the
IGBT after the fault and to reduce the overvoltage due to
the turn-off
The purpose is to control the overvoltage
caused by the parasitic inductance of the power circuit while
turning off large currents.
This paper focuses on the following study issues for active
protection of fault currents for IGBT modules.
• Use of a large on-state gate voltage to reduce conduction
losses makes the fault situation more problematic and
dangerous, because it leads to very high fault current. This
results in large instantaneous power dissipation [13] and
the possibility of latching in the device. Therefore, there
is a tradeoff between the short-circuit current magnitude
and the conduction loss.
• Precise detection of fault current levels is a challenging
issue if current sensors are not used in series with the
IGBT’s. In particular, in case of large fault inductance
(soft fault) it is difficult to precisely recognize the over-
current condition using the de-saturation technique, which
is a common method used to identify a fault situation.
This is due to the reduced voltage drop in the IGBT under
low
conditions, as well as the slow dynamics in the
electronic components in the detection circuit.
• Fast detection and reliable handling of fault currents are
important study issues. The initial value of short current is
the highest due to the increased gate voltage caused by the
Miller capacitance. It is not easy to reduce the initial peak
current, because activation of protection circuit should be
prevented during the turn-on transient conditions of the
IGBT, and during noise phenomena caused by the IGBTs’
switching in the power converter;
• At shutdown, the falling rate of the current should be con-
trolled to reduce the overvoltage stress. The overvoltage
level across the device can become much larger than the
rated voltage, if the large collector current is turned off
without any treatment. While using an FCLC, soft turn-off
0093–9994/99$10.00 1999 IEEE
478 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 35, NO. 2, MARCH/APRIL 1999
requires one to take into account possible changes in the
operating modes of the protection circuit.
For the study mentioned above, experimental investigation
on the fault situation is performed in detail for the cases of
variation of temperature, rising rate of fault current, positive
gate voltage level, and circuit parameters. A new active
protection method is proposed, which can limit fault currents
to a reasonable level while suppressing the initial peak current
value and safely shut down the IGBT. Test results are given by
using IGBT’s from different manufacturers to study operation
of the protection circuit under varying device parameters.
II. O
PERATION CHARACTERISTICS OF THE
PROPOSED ACTIVE PROTECTION CIRCUIT
Fast detection of the occurrence of the fault, limiting of
the initial peak current, clamping of the overcurrent, and safe
shutdown are essential features of the protection circuit. The
types of short-circuit faults that can occur in an IGBT can be
classified as hard-switched fault (HSF) and fault under load
(FUL) [14]. HSF occurs when the IGBT tries to turn on into
a short circuit. FUL is the case where the short circuit occurs
when the IGBT is in the on state conducting normal load
current. Fig. 1 shows the schematic of the proposed circuit,
which is composed of the basic drive circuit, the additional
protective control circuit, and the three feedback lines, which
are collector voltage detection, collector desaturation voltage,
and power emitter voltage. Functions and operational charac-
teristics of the circuit are explained.
A. Detection
The detection of fault current is based on two inputs into
the protection control circuit. One is the collector to emitter
voltage of the device of the IGBT, which is a function of the
collector current in the device. A diode is used to clamp this
voltage below the positive gate drive power supply voltage,
and is called the collector desaturation voltage. The other is
the voltage drop between the power and the Kelvin emitter
terminal of the device. In an IGBT module, the Kelvin emitter
terminal is available externally, because the gate signal is
applied between the gate and Kelvin emitter terminals. If we
look at the voltage between the power emitter and the Kelvin
emitter, we can monitor the voltage drop in the connection
inductance between the external power emitter terminal and
its internal semiconductor contact, which is caused by the
collector current. Here, the Kelvin emitter terminal can be
considered as the semiconductor contact point. The inductance
is of the order of a few nanohenrys and becomes larger in
higher power modules due to longer distances between the
semiconductor and the power emitter terminal. This allows
an estimate of the IGBT collector current level, which is
obtained using a resettable integrator circuit shown in Fig. 1.
The parameters of the integrator are based on the connection
inductance between the two emitter terminals, the loading of
the integrator circuit, and parasitic capacitance of the reset
switch. The desaturation voltage detection has a rapid response
to low impedance (hard fault) FUL condition. The device
current estimator is more effective in detecting soft fault
Fig. 1. Schematic diagram of the proposed protection circuit.
Fig. 2. Test setup.
situations. Direct measurement circuit of the collector voltage,
which is added to collector feedback line in Fig. 1, is used
to rapidly recognize HSF condition and to distinguish it from
normal switching transients of the IGBT [12].
B. Limiting
Limiting of the current is obtained using the capacitor
and the zener diode for fast and stable protection. On detec-
tion of the fault, the transistor
is turned on, which causes
to charge up to the voltage level of thus discharging
the gate. The transistor is activated by the combination of the
collector current estimate and the desaturation voltage, which
is obtained using diodes
and A large results in
initial oscillation in the device current and a slow ramp up
JOHN et al.: FAST-CLAMPED SHORT-CIRCUIT PROTECTION OF IGBT’S 479
(a) (b)
Fig. 3. FUL test results for IGBT1 under
V
ge
variation. (a) Without protection. (b) With protection. Selected positive gate voltages are as follows: 14, 15,
16, 17, 18, and 19V. Other conditions are as follows:
C
1
=
30
nF, precharge voltage
=
4.5 V,
V
dc
=405
V,
T
=24
C,
L
= 200
nH.
(a) (b)
Fig. 4. HSF test results for IGBT1 under
V
ge
variation. (a) Without protection. (b) With protection. Selected positive gate voltages are as follows: 14, 15,
16, 17, 18, and 19 V. Other conditions are as follows:
C
1
=60
nF, precharge voltage
=5
V,
V
dc
= 405
V,
T
=24
C,
L
= 200
nH.
to the clamp current level. A small value of results in an
increased peak fault current due to insufficient gate discharge.
The zener diodes
and make the voltage of be at
the desired voltage level before turning on the IGBT. This
precharge voltage compensates for the delay in operation of
the protection circuit. A lower precharge voltage will result
in the activation of the protection circuit at an earlier instant.
The on-state voltage of the IGBT and the voltage drop along
the desaturation detection circuit limit the minimum value of
the precharge voltage.
C. Clamping
The final gate voltage level is clamped by the zener
The value of the zener voltage is selected to be above the
threshold voltage and depends on the transconductance gain
of the driven IGBT. The voltage drops across the transistor
and the diode have to be considered while selecting
the zener diode
The clamped gate voltage decides the
clamped level of fault current.
D. Shutdown
The capacitor
is placed in parallel with the gate capaci-
tance to turn off the IGBT at a reduced
The collector
voltage detection signal provides information to the power
converter control circuits about occurrence of the fault and
initiates the safe shutdown. The current path changes from
-
- during clamping mode to - - during shutdown.
The precharge level of
is higher than the gate voltage level
used for clamping due to the voltage drop corresponding to the
conducting paths of the shutdown circuit. This eliminates the
small notch in gate voltage caused by the reversal of current
from the clamping mode to the safe shutdown mode. The
purpose of the diode
is to obtain decoupling between the
precharge voltage levels for
and The zener diode
determines the precharge level of
E. Fault Monitoring
Nuisance faults signals can be rejected strongly because the
main fault signal sent to the system controller occurs based
480 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 35, NO. 2, MARCH/APRIL 1999
(a) (b)
Fig. 5. Effect of variation of on-state gate voltage on fault parameters. (a) Use of IGBT2 with the operating conditions—FUL:
C
1
=
30
nF, precharge
=5
V; HSF:
C
1
=20
nF, pre-charge
=3
:
45
V;
V
dc
= 405
V,
T
=24
C,
L
= 200
nH. (b) Use of IGBT3 with the operating conditions—FUL:
C
1
=60
nF, precharge
=5
V; HSF:
C
1
=30
nF, precharge
=6
V;
V
dc
= 405
V,
T
=24
C,
L
= 200
nH.
(a) (b)
Fig. 6. FUL test results for IGBT1 under variation of temperature. (a) Without protection. (b) With protection. Selected temperatures are as follows:24
C,
40
C, 60
C, 90
C, and 120
C. Other conditions are as follows:
C
1
=60
nF, precharge voltage
=5
V,
V
dc
= 405
V,
V
ge
=15
V,
L
= 200
nH.
on the measured information. Also, a delay time of a few
microseconds is used to report the fault information allowing
for momentary transient in the current that could occur without
damaging the device. These momentary transients are also held
to the clamping current level.
III. E
XPERIMENTAL EVALUATION
A simple test circuit is set up to verify the validity of the
proposed protection circuit, which is shown in Fig. 2. A two-
pulse method has been used to drive the IGBT with an inductor
as the load. The controlled time duration for the first pulse is
for obtaining the desired load current, which would be the
initial value at turn on of the second pulse. For testing under
FUL conditions, the short-circuit control switch in Fig. 2 is
turned on while the device under test (DUT) is in on state and
conducting load current during the second pulse. On the other
hand, for HSF test, the short-circuit control switch is already
turned on before the second pulse activates the DUT. The test
has been conducted with three different dual IGBT modules:
IGBT1: Toshiba MG100Q2YS40 (1200 V, 100 A); IGBT2:
Powerex CM75DY-12H (600 V, 75 A); and IGBT3: Fuji
2MBI75-060 (600 V, 75 A). The measured collector current,
JOHN et al.: FAST-CLAMPED SHORT-CIRCUIT PROTECTION OF IGBT’S 481
(a) (b)
Fig. 7. HSF test results for IGBT1 under variation of temperature. (a) Without protection. (b) With protection. Selected temperatures are as follows:24
C,
40
C, 60
C, 90, and 120
C. Other conditions are as follows:
C
1
=
30
nF, precharge voltage
=4
:
5
V,
V
dc
= 405
V,
V
ge
=15
V,
L
= 200
nH.
(a) (b)
Fig. 8. Effect of variation of temperature on fault parameters. (a) Use of IGBT2 with the operating conditions—FUL:
C
1
=30
nF, precharge
=5
V;
HSF:
C
1
=20
nF, precharge
=3
:
45
V;
V
dc
= 405
V,
V
ge
=15
V,
L
= 200
nH. (b) Use of IGBT3 with the operating conditions—FUL:
C
1
=60
nF, precharge
=5
V; HSF:
C
1
=30
nF, pre-charge
=6
V;
V
dc
= 405
V,
V
ge
=15
V,
L
= 200
nH.
collector voltage, and gate voltage waveforms for IGBT1, and
graphs of the peak current and the clamped current levels for
IGBT’s 2 and 3 for the cases of with and without protection
are shown.
A. On-State Gate Voltage Variation
Fig. 3(a) and (b) shows the test results of FUL while varying
the on-state gate voltage, which is the parameter studied during
this test. In the case of no protection shown in Fig. 3(a), the
peak and the final current levels are strongly dependent on the
gate voltages. When the on-state gate voltage is 19 V, the peak
current is more than 15 times the rated current. There is not
much difference in the
waveform. From Fig. 3(b), it can
be seen that fault currents are at controlled levels, irrespective
of the on-state gate voltage with the active protection circuit.
Fig. 4(a) and (b) is for the case of HSF. Fig. 4(b) shows
that the protection circuit keeps fault currents within a small
envelope for a wide range of the on-state gate voltage levels,
as in the case of FUL. On the other hand, from Fig. 4(a), it is
shown that the peak and the final current levels increased by a
factor of two when the gate voltage was increased from 14 to
19 V. The waveforms in Figs. 3(b) and 4(b) use the selected
values of
and the precharge voltage that result in optimal
characteristics of the protection circuit. The tradeoff involved
when these parameters are changed is explained in Sections
III-D and III-E.The graphs of the key parameters, while using
