Book ChapterDOI
Fault Detection and Design For Testability of CMOS Logic Circuits
Sudhakar M. Reddy,Sandip Kundu +1 more
- pp 69-91
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TLDR
Some of the basic methods and issues related to the design and fault detection of CMOS logic circuits are reviewed.Abstract:
Advances in integrated circuit technologies have made complementary MOS (CMOS) the preferred MOS technology for digital logic circuits. Cost effective design and fabrication of reliable CMOS VLSI chips require understanding of various CMOS technologies, logic families, failure modes, fault detection methods and design for testability methods. In this paper we will review some of the basic methods and issues related to the design and fault detection of CMOS logic circuits.read more
Citations
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Proceedings ArticleDOI
CMOS IC stuck-open-fault electrical effects and design considerations
TL;DR: The measured transient response of stuck-open faults shows that this defect acts as a memory fault for normal system and tester clock periods and that detectable elevated I/sub DDQ/ can occur rapidly for some circuit designs.
Journal ArticleDOI
Designing CMOS Circuits for Switch-Level Testability
Dick L. Liu,Edward J. McCluskey +1 more
TL;DR: The design techniques presented here for fully testable CMOS combinational circuits use a three-pattern test scheme to detect both stuck-open and stuck-on switch-level faults.
Book ChapterDOI
On the design of robust multiple fault testable CMOS combinational logic circuits
TL;DR: In this paper, the authors present a robust test for combinational logic circuits in which all stuck-at and stuck-open and multipath delay faults are robustly testable.
Journal ArticleDOI
A minimal universal test set for self-test of EXOR-Sum-of-Products circuits
TL;DR: A testable EXOR-Sum-of-Products (ESOP) circuit realization and a simple, universal test set which detects all single stuck-at faults in the internal lines and the primary inputs/ outputs of the realization are given.
Journal ArticleDOI
Design of robustly testable combinational logic circuits
TL;DR: An integrated approach to the design of combinational logic circuits in which all path delay faults and multiple line stuck-at, transistor stuck-open faults are detectable by robust tests is proposed.
References
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Journal ArticleDOI
Fault modeling and logic simulation of CMOS and MOS integrated circuits
TL;DR: This paper provides a methodology for creating simulator models for tri-state and other dynamic circuit elements that provide for both classical and stuck-open/stuck-on faults, and can be adopted for use on essentially any general purpose logic simulator.
Journal ArticleDOI
Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability
Galiay,Crouzet,Vergniault +2 more
TL;DR: At the end of an IC production line, integrated circuits are generally submitted to three kinds of tests: 1) parametric tests to check electrical characteristics (voltage, current, power consumption), 2) dynamic tests to Check response times under nominal operating conditions, and 3) functional tests toCheck its logical behavior.
Journal ArticleDOI
Easily Testable Realizations ror Logic Functions
TL;DR: A realization for arbitrary logic function, using AND and EXCLUSIVE-OR gates, based on Reed-Muller canonic expansion is given that has many of these desirable properties of "easily testable networks".
Proceedings ArticleDOI
Test Generation for MOS Circuits Using D-Algorithm
TL;DR: An application of the D-algorithm in generating tests for MOS circuit faults is described, which includes modeling and test generation for combinational and acyclic MOS circuits that may contain transmission gates and buses.
Journal ArticleDOI
Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits
TL;DR: It is shown that all single FET stuck-open faults, in a specific design using a single CMOs complex gate, are detectable by tests that remain valid in the presence of arbitrary circuit delays.