Journal ArticleDOI
Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits
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TLDR
It is shown that all single FET stuck-open faults, in a specific design using a single CMOs complex gate, are detectable by tests that remain valid in the presence of arbitrary circuit delays.Abstract:
In this paper, potential invalidation of stuck-open fault-detecting tests, derived by neglecting circuit delays and charge distribution in CMOS logic circuits, is studied. Several classes of circuits derived from sum of products and product of sums expressions for a given combinational logic function are investigated to determine the testability of FET stuck-open faults by tests which will remain valid in the presence of arbitrary circuit delays. Necessary and sufficient conditions for the existence of tests that will remain valid in the presence of arbitrary circuit delays are derived. Using these conditions, it is shown that all single FET stuck-open faults, in a specific design using a single CMOs complex gate, are detectable by tests that remain valid in the presence of arbitrary circuit delays. For several other realizations, methods to augment them, to insure detectability of all single FET stuck-open faults by tests that will remain valid in the presence of arbitrary circuit delays are proposed. It is observed that in many of the logic circuits investigated it is also possible to avoid test invalidation due to charge distribution.read more
Citations
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Book
Iddq Testing for CMOS VLSI
TL;DR: Iddq testing has been widely used in the field of semiconductor testing as discussed by the authors and many semiconductor companies now consider Iddq test as an integral part of the overall testing for all IC's.
Proceedings ArticleDOI
A cell-replicating approach to minicut-based circuit partitioning
C. Kring,A.R. Newton +1 more
TL;DR: An extension to the Fiduccia and Mattheyses minicut algorithm (1982) allows cells to be replicated in both sides of the partition and can substantially reduce the number of cut nets in a partitioned network below what can be obtained without replication.
Proceedings ArticleDOI
On the design of robust testable CMOS combinational logic circuits
Sandip Kundu,Sudhakar M. Reddy +1 more
TL;DR: The authors propose an integrated approach to the design of combinational logic circuits in which stuck-open faults and path delay faults are detectable by robust tests that detect modeled faults independent of the delays in the circuit under test.
Journal ArticleDOI
Detecting FET Stuck-Open Faults in CMOS Latches And Flip-Flops
TL;DR: Evidence that conventional tests cannot detect FET stuck-open faults in several CMOS latches and flip-flops is presented, and designs are given for several memory devices that can be used in applications requiring static memory elements whose operation can be reliably ascertained through conventional fault testing methods.
Book ChapterDOI
On the design of robust multiple fault testable CMOS combinational logic circuits
TL;DR: In this paper, the authors present a robust test for combinational logic circuits in which all stuck-at and stuck-open and multipath delay faults are robustly testable.
References
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Fault modeling and logic simulation of CMOS and MOS integrated circuits
TL;DR: This paper provides a methodology for creating simulator models for tri-state and other dynamic circuit elements that provide for both classical and stuck-open/stuck-on faults, and can be adopted for use on essentially any general purpose logic simulator.
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High-speed compact circuits with CMOS
TL;DR: A new circuit type, the CMOS domino circuit, is described, which involves the connection of dynamic CMOS gates in such a way that a single clock edge can be used to turn on all gates in the circuit at once.
Journal ArticleDOI
Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability
Galiay,Crouzet,Vergniault +2 more
TL;DR: At the end of an IC production line, integrated circuits are generally submitted to three kinds of tests: 1) parametric tests to check electrical characteristics (voltage, current, power consumption), 2) dynamic tests to Check response times under nominal operating conditions, and 3) functional tests toCheck its logical behavior.
Journal ArticleDOI
Design for Autonomous Test
McCluskey,Bozorgui-Nesbat +1 more
TL;DR: A technique for modifying networks so that they are capable of self test is presented, partitioning the network into subnets with sufficiently few inputs that exhaustive testing of the subnetworks is possible.