Journal ArticleDOI
Functional Level Primitives in Test Generation
TLDR
The concept of solution sequences to test problems for primitive elements is introduced and a functional language used to describe solution sequences is presented, including procedures for implication, D-drive and line justification.Abstract:
This paper deals with the use and development of high-level (functional) primitive logic elements for use in a system which automatically generates tests for complex sequential circuits. The concept of solution sequences to test problems for primitive elements is introduced and a functional language used to describe solution sequences is presented. Functional test generation models for two basic elements, a shift register and a counter, are derived, including procedures for implication, D-drive and line justification. Primitive algorithms which generate single as well as multivector (sequences) solutions to D-drive and line justification problems are presented.read more
Citations
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Journal ArticleDOI
Functional Testing of Semiconductor Random Access Memories
TL;DR: An overview of the problem of testing semiconductor random access memories (RAMs) and several fault models, including the stuck-at-0/1 faults, coupled-cell faults, and single-cell pattern-sensitive faults are presented.
Journal ArticleDOI
Diagnosis and reliable design of digital systems
TL;DR: It's coming again, the new collection that this site has, and the favorite diagnosis and reliable design of digital systems book is offered as the choice today.
Journal ArticleDOI
Hierarchical test generation using precomputed tests for modules
B.T. Murray,John P. Hayes +1 more
TL;DR: A novel test generation technique for large circuits with high fault coverage requirements is described and preliminary results suggest that for circuits composed of datapath elements, speed improvements of three orders of magnitude over conventional techniques may be possible.
Journal ArticleDOI
Testing of digital systems
TL;DR: This paper is intended to be both a tutorial on hardware testing and a brief survey of existing techniques, with special emphasis on those that have gained wide acceptance.
Proceedings ArticleDOI
Hierarchical test generation using precomputed testsd for modules
B.T. Murray,John P. Hayes +1 more
TL;DR: A novel test-generation technique for large circuits with high fault-coverage requirements is described, which shows that a substantial increase in test generation speed can be achieved.
References
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Journal ArticleDOI
Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic Circuits
TL;DR: Two algorithms are presented: one, DALG-II, computes a test to detect a failure in acyclic logic circuits; the other, TEST-DETECT, ascertains all failures detected by a given test.
Journal ArticleDOI
Diagnosis and reliable design of digital systems
TL;DR: It's coming again, the new collection that this site has, and the favorite diagnosis and reliable design of digital systems book is offered as the choice today.
Journal ArticleDOI
A Note on Three-Valued Logic Simulation
TL;DR: The areas covered include hazard and race detection, fault detection, verifying the reset logic of a machine, and the problems encountered with self-timing circuits and in employing a complement for u.
Proceedings ArticleDOI
Concurrent fault simulation and functional level modeling
TL;DR: This paper discusses some of the major issues dealing with the design of a functional level concurrent fault simulator for digital net works, and presents the major attributes of an abstract data structure required for this system.