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Guaranteed in-order packet delivery using Exclusive Dynamic Virtual Channel Allocation

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TLDR
Exclusive Dynamic VCA is presented, an oblivious virtual channel allocation scheme which combines the performance advantages of dynamic virtual allocation with in-network, deadlock-free in-order delivery, and reduces head-of-line blocking.
Abstract
In-order packet delivery, a critical abstraction for many higher-level protocols, can severely limit the performance potential in low-latency networks (common, for example, in network-on-chip designs with many cores). While basic variants of dimension-order routing guarantee in-order delivery, improving performance by adding multiple dynamically allocated virtual channels or using other routing schemes compromises this guarantee. Although this can be addressed by reordering out-of-order packets at the destination core, such schemes incur significant overheads, and, in the worst case, raise the specter of deadlock or require expensive retransmission. We present Exclusive Dynamic VCA, an oblivious virtual channel allocation scheme which combines the performance advantages of dynamic virtual allocation with in-network, deadlock-free in-order delivery. At the same time, our scheme reduces head-of-line blocking, often significantly improving throughput compared to equivalent baseline (out-of-order) dimension-order routing when multiple virtual channels are used, and so may be desirable even when in-order delivery is not required. Implementation requires only minor, inexpensive changes to traditional oblivious dimension-order router architectures, more than offset by the removal of packet reorder buffers and logic.

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Proceedings ArticleDOI

Scalable, accurate multicore simulation in the 1000-core era

TL;DR: HORNET, a parallel, highly configurable, cycle-level multicore simulator based on an ingress-queued worm-hole router NoC architecture, offers cycle-accurate as well as periodic synchronization; while preserving functional accuracy, this permits tradeoffs between perfect timing accuracy and high speed with very good accuracy.

Darsim: A Parallel Cycle-Level NoC Simulator

TL;DR: DARSIM is a parallel, highly configurable, cycle-level network-on-chip simulator based on an ingress-queued wormhole router architecture that allows a variety of routing and virtual channel allocation algorithms out of the box, ranging from simple DOR routing to complex Valiant, ROMM, or PROM schemes, BSOR, and adaptive routing.
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HORNET: A Cycle-Level Multicore Simulator

TL;DR: Hornet, a parallel, highly configurable, cycle-level multicore simulator based on an ingress-queued wormhole router network-on-chip (NoC) architecture, offers cycle-accurate as well as periodic synchronization; while preserving functional accuracy, this permits tradeoffs between perfect timing accuracy and high speed with very good accuracy.
Journal ArticleDOI

A Bidirectional NoC (BiNoC) Architecture With Dynamic Self-Reconfigurable Channel

TL;DR: Novel on-chip router architecture is developed to support dynamic self-reconfiguration of the bidirectional traffic flow and exhibits consistent and significant performance advantage over conventional NoC equipped with hard-wired unidirectional channels.
Proceedings ArticleDOI

DyXYZ: Fully Adaptive Routing Algorithm for 3D NoCs

TL;DR: This paper presents a fully adaptive routing algorithm for 3D NoCs, named DyXYZ, which is proven to be deadlock free by using 4, 4, and 2 virtual channels along the X, Y, and Z dimensions, respectively.
References
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Book

Principles and Practices of Interconnection Networks

TL;DR: This book offers a detailed and comprehensive presentation of the basic principles of interconnection network design, clearly illustrating them with numerous examples, chapter exercises, and case studies, allowing a designer to see all the steps of the process from abstract design to concrete implementation.
Journal ArticleDOI

Deadlock-Free Message Routing in Multiprocessor Interconnection Networks

TL;DR: In this article, a deadlock-free routing algorithm for arbitrary interconnection networks using the concept of virtual channels is presented, where the necessary and sufficient condition for deadlock free routing is the absence of cycles in a channel dependency graph.
Book

Deadlock-free message routing in multiprocessor interconnection networks

TL;DR: A deadlock-free routing algorithm can be generated for arbitrary interconnection networks using the concept of virtual channels, which is used to develop deadlocked routing algorithms for k-ary n-cubes, for cube-connected cycles, and for shuffle-exchange networks.
Book

Computer Architecture, Fifth Edition: A Quantitative Approach

TL;DR: The Fifth Edition of Computer Architecture focuses on this dramatic shift in the ways in which software and technology in the "cloud" are accessed by cell phones, tablets, laptops, and other mobile computing devices.