Open AccessJournal Article
High Speed Pulse-based Flip-Flop with Pseudo MUX-type Scan for Standard Cell Library
Min-Su Kim,Sang-Shin Han,Chae Kyoung-Kuk,Chung-hee Kim,Gunok Jung,Kwang-Il Kim,Jinyoung Park,Youngmin Shin,Sung-Bae Park,Young-Hyun Jun,Bai-Sun Kong +10 more
TLDR
In this article, a high-speed pulse-based flip-flop with pseudo MUX-type scan compatible with the conventional master-slave flip flop with MUX type scan was implemented as the standard cell library using 130㎚ HS technology.Abstract:
This paper presents a high-speed pulse-based flip-flop with pseudo MUX-type scan compatible with the conventional master-slave flip-flop with MUX-type scan. The proposed flip-flop was implemented as the standard cell library using Samsung 130㎚ HS technology. The data-to-output delay and power-delay-product of the proposed flip-flop are reduced by up to 59% and 49%, respectively. By using this flop-flop, ARM11 softcore has achieved the maximum 1㎓ operating speed.read more
Citations
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An On-Chip Test Clock Control Scheme for Circuit Aging Monitoring
TL;DR: This paper describes limitations of existing at-speed test clock control methods and presents an on-chip faster-than-at-speedTest clock control scheme for intra/inter-clock domain test and shows experimental results.
References
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Proceedings ArticleDOI
A 1.5 GHz 90 nm embedded microprocessor core
Franco Ricci,L.T. Clark,Timothy S. Beatty,Wing K. Yu,A. Bashmakov,Shay Demmons,E. Fox,Jeffrey L. Miller,M. Biyani,J.R. Haigh +9 more
TL;DR: A 90 nm ARM/spl trade/ V5TE compatible microprocessor core intended for high performance and low power embedded applications is described, which includes an ECC protected 2 level 512 MB cache.
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Optimization of scannable latches for low energy
TL;DR: This paper revisits, extends, and improves the energy-performance optimization methodology, attempting to make it more formal and comprehensive, and proposes a low-power level-sensitive scan mechanism for latches, and results of a comparative study of scannable latches are shown.
Proceedings ArticleDOI
Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits
J.P. Hurst,N. Kanopoulos +1 more
TL;DR: Flip-flop sharing modifies the order of the flip-flops in the scan path such that adjacent flip- flops along the path are from different sequential machines, which allows the application of arbitrary two-vector test sets necessary for delay fault testing.
Journal Article
Nanoscale Floating-Gate Characteristics of Colloidal Au Nanoparticles Electrostatically Assembled on Si Nanowire Split-Gate Transistors
Hyeong-Seok Jeon,Bonghyun Park,Chi-Won Cho,Chaehyun Lim,Heongkyu Ju,Hyun-Suk Kim,Sangsig Kim,Seung-Beck Lee +7 more
TL;DR: In this paper, the nanoscale floating-gate characteristic of colloidal Au nanoparticles electrostatically assembled on the oxidized surface of Si nanowires has been investigated.