IBM PowerNP network processor: Hardware, software, and applications
read more
Citations
Linear Types for Packet Processing
Parallel data link layer controllers in a network switching device
Leaping Multiple Headers in a Single Bound: Wire-Speed Parsing Using the Kangaroo System
Multiprocessor subsystem in SoC with bridge between processor clusters interconnetion and SoC system bus
Packet processor with wide register set architecture
References
IP Mobility Support
Algorithms for packet classification
A Two Rate Three Color Marker
A Single Rate Three Color Marker
Building a robust software-based router using network processors
Related Papers (5)
Frequently Asked Questions (16)
Q2. What is the importance of a unified packet-based network?
Scalability for traffic engineering, quality of service (QoS), and the integration of wireless networks in a unified packet-based next-generation network requires traffic differentiation and aggregation.
Q3. How many cycles per second can the egress DS run?
To sustain media speed with 48-byte packets, 6.1 million packets per second, the egress DS must run with a 10-clock cycle data store access window.
Q4. What are the main components of the PowerNP?
The PowerNP has the following main components: embedded processor complex (EPC), data flow (DF), scheduler, MACs, and coprocessors.
Q5. What is the function of the control store arbiter?
The control store arbiter (CSA) controls access to the control store (CS), which allocates memory bandwidth among the threads of all DPPUs.
Q6. What is the way to ensure consistency in the assignment and verification of GTP sequence numbers?
Consistency in the assignment and verification of GTP sequence numbers, and in operations on the reordering queues, is ensured by using the semaphore coprocessor.
Q7. How many threads can be executed simultaneously?
Although there are 32 independent threads, each CLP can execute the instructions of only one of its threads at a time, so at any instant up to 16 threads are executing simultaneously.
Q8. What is the purpose of the DS interface and arbiters?
The ingress and egress DS interface and arbiters are for controlling accesses to the DS, since only one thread at a time can access either DS.
Q9. What is the way to configure a DMU for Gigabit Ethernet?
To support 1 Gigabit Ethernet, a DMU can be configured as either a gigabit mediaindependent interface (GMII) or a ten-bit interface (TBI).
Q10. Why is it easier to develop new high-performance applications?
Because of the availability of associated advanced development and simulation tools, combined with extensive reference implementations, rapid prototyping and development of new high-performance applications are significantly easier than with either GPPs or ASICs.
Q11. What is the softwarearchitecture and programming model?
The softwarearchitecture and programming model describes the data plane functions and APIs, the control plane functions and APIs, and the communication model between these components.
Q12. What are the types of threads supported in the EPC?
Five types of threads are supported:● General data handler (GDH) Seven DPPUs contain the GDH threads for a total of 28 GDH threads.
Q13. What is the abbreviation of the term PowerNP?
In this paper the abbreviated term PowerNP is used to designate the IBM PowerNP NP4GS3, which is a high-end member of the IBM network processor family.
Q14. What is the assembler for creating images designed to execute on the powerNP?
It generates files used to execute picocode on the chip-level simulation model or the PowerNP, as well as files that picocode programmers can use for debugging.
Q15. What is the main structure that manages the CS?
The lookup definition table (LuDefTable), an internal memory structure that contains 128 entries to define 128 trees, is the main structure that manages the CS.
Q16. What is the significant challenge of a pipelined programming model?
Perhaps a more significant challenge of a pipelined programming model is in dealing with changes, since a relatively minor code change may require a programmer to start from scratch with code partitioning.