Proceedings ArticleDOI
PacketBench: a tool for workload characterization of network processing
Ramaswamy Ramaswamy,Tilman Wolf +1 more
- pp 42-50
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TLDR
A tool called PacketBench is presented, which provides a framework for implementing network processing applications and obtaining an extensive set of workload characteristics, and the results show that such workload analysis has a range of uses from network processor design to application optimization.Abstract:
Network processing is becoming an increasingly important paradigm as the Internet moves towards an architecture with more complex functionality inside the network. Modern routers not only forward packets, but also process headers and payloads to implement a variety of functions related to security, performance, and customization. It is important to get a detailed understanding of the workloads associated with this processing in order to be able to develop efficient network processing engines. We present a tool called PacketBench, which provides a framework for implementing network processing applications and obtaining an extensive set of workload characteristics. PacketBench provides the support functions to handle various packet traces and manage packet memory. For statistics collection, PacketBench provides the ability to derive a number of microarchitectural and networking related metrics. We present the results of such measurements for four different networking applications ranging from simple packet forwarding to complex packet payload encryption. The results show that such workload analysis has a range of uses from network processor design to application optimization.read more
Citations
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Proceedings ArticleDOI
Characterizing network processing delay
TL;DR: This work evaluates different network applications and develops a model that characterizes packet processing cost with only a few parameters that can easily be derived from network simulations, and compares them to actual network measurements.
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TAPES--Trace-based architecture performance evaluation with SystemC
TL;DR: TAPES (Trace-based Architecture Performance Evaluation with SystemC), an approach that supports system designers in the performance evaluation of SoC architectures that uses SystemC as modeling language, requires low modeling effort and yet provides accurate results within reasonable turnaround times.
Pipelining vs. Multiprocessors – Choosing the Right Network Processor System Topology
TL;DR: A mechanism for mapping the workload optimally to an arbitrary topology based on run-time traces is presented and results from several NP applications are presented, showing the performance tradeoffs between different system topology, and identifying system bottlenecks.
Proceedings ArticleDOI
An ILP formulation for system-level application mapping on network processor architectures
Chris Ostler,Karam S. Chatha +1 more
TL;DR: An automated system-level design technique for application development on current day network processors that incorporates process transformations and block multi-threading aware data mapping to maximize the worst case throughput of the application.
Proceedings ArticleDOI
Reliability-aware design for nanometer-scale devices
David Atienza,G. De Micheli,Luca Benini,José L. Ayala,P.G. Del Valle,Michael DeBole,Vijaykrishnan Narayanan +6 more
TL;DR: This paper illustrates with a case study of an embedded processor that effective reliability-aware design can be achieved in nanometer-scale devices through integral design approaches that covers modeling and exploration of reliability effects, and hardware-software architectural techniques to provide reliability-enhanced solutions at both microarchitectural- and system-level.
References
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Security Architecture for the Internet Protocol
TL;DR: This document describes an updated version of the "Security Architecture for IP", which is designed to provide security services for traffic at the IP layer, and obsoletes RFC 2401 (November 1998).
Journal ArticleDOI
The SimpleScalar tool set, version 2.0
Doug Burger,Todd Austin +1 more
TL;DR: This document describes release 2.0 of the SimpleScalar tool set, a suite of free, publicly available simulation tools that offer both detailed and high-performance simulation of modern microprocessors.
Journal ArticleDOI
A survey of active network research
TL;DR: It is illustrated how the routers of an IP network could be augmented to perform such customized processing on the datagrams flowing through them, and these active routers could also interoperate with legacy routers, which transparently forwarddatagrams in the traditional manner.
Journal ArticleDOI
A security architecture for the Internet protocol
TL;DR: The design, rationale, and implementation of a security architecture for protecting the secrecy and integrity of Internet traffic at the Internet Protocol (IP) layer, which includes a modular key management protocol, called MKMP, is presented.
The IP Network Address Translator (NAT)
K. Egevang,Paul Francis +1 more
TL;DR: The two most compelling problems facing the IP Internet are IP address depletion and scaling in routing and the short-term solution is CIDR (Classless InterDomain Routing).