Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-on-Chip
J.-Y. Mignolet,V. Nollet,Paul Coene,Diederik Verkest,Serge Vernalde,Rudy Lauwereins +5 more
- pp 10986-10993
TLDR
The general scope of the research is presented, and the communication scheme, the design environment and the hardware/software context switching issues are details, which proved its feasibility by allowing us to design a relocatable video decoder.Abstract:
The ability to (re)schedule a task either in hardware or software will be an important asset in a reconfigurable systems-on-chip. To support this feature we have developed an infrastructure that, combined with a suitable design environment permits the implementation and management of hardware/software relocatable tasks. This paper presents the general scope of our research, and details the communication scheme, the design environment and the hardware/software context switching issues. The infrastructure proved its feasibility by allowing us to design a relocatable video decoder. When implemented on an embedded platform, the decoder performs at 23 frames/s (320/spl times/240 pixels, 16 bits per pixel) in reconfigurable hardware and 6 frames/s in software.read more
Citations
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Proceedings ArticleDOI
An FPGA run-time system for dynamical on-demand reconfiguration
TL;DR: This contribution presents a first approach for a flexible versatile FPGA-based run-time system supporting a resource saving function multiplex for a growing number of engine control units.
Patent
Heterogeneous multiprocessor network on chip devices, methods and operating systems for control thereof
Vincent Nollet,Paul Coene,Theodore Marescaux,Prabhat Avasare,Jean-Yves Mignolet,Serge Vernalde,Diederik Verkest +6 more
TL;DR: In this paper, the authors describe a network on chip (NoC) device with Reconfigurable Hardware Tiles (RHET) and an Operating System (OS) for controlling it.
Proceedings ArticleDOI
Context saving and restoring for multitasking in reconfigurable systems
H. Kalte,Mario Porrmann +1 more
TL;DR: This paper discusses ways to save and restore the state information of a hardware task, and significantly reduces the amount of readback data by reading only those configuration frames that contain state information.
Proceedings ArticleDOI
Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles
TL;DR: It is shown that specific reconfigurable hardware support improves the performance of the heuristic and that task migration mechanisms need to be tailored to on-chip networks.
Proceedings ArticleDOI
Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration
TL;DR: A method is introduced that circumvents the problem of having to find fully identical regions based on compatible subsets of resources, enabling flexible placement of relocatable modules on the FPGA.
References
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JBits: Java based interface for reconfigurable computing
TL;DR: The JBitsTM software is a set of JavaTM classes which provide an Application Programming Interface (API) to access the Xilinx FPGA bitstream, which permits all configurable resources like Look-up tables, routing and the flip-flops in the FPN to be individually configured under software control.
Book ChapterDOI
Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs
Théodore Marescaux,Andrei Bartic,Diederik Verkest,Diederik Verkest,Serge Vernalde,Rudy Lauwereins,Rudy Lauwereins +6 more
TL;DR: This paper explains how separating communication from computation enables hardware multi-tasking and describes the implementation of a fixed communication-layer that decouples the computation elements, allowing them to be dynamically reconfigured.
Proceedings ArticleDOI
A dynamic reconfiguration run-time system
TL;DR: This work presents the design of an extensible run-time system for managing the dynamic reconfiguration of FPGAs, called RAGE, and incorporates operating-system style services that permit sophisticated and high level operations on circuits.
Book ChapterDOI
Multitasking on FPGA Coprocessors
TL;DR: The control software required to support task switching for an application split over the host processor - coprocessor boundary as well as the requirements and features of context saving and restoring in the FPGA cop rocessor context are explored.
Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform
TL;DR: This paper investigates placement techniques for non-rectangular, coarsegrained tasks and proposes footprint transforms that change task shapes in order to find possible mappings and discusses simulation experiments to evaluate these techniques.