Patent
Integrated logic circuit having interconnections of various lengths between field effect transistors of enhancement and depletion modes
TLDR
In this article, an integrated logic circuit includes an array of insulated gate field effect transistors formed at the crossings of a plurality of substantially parallel first conductor tracks and strip-shaped surface regions.Abstract:
An integrated logic circuit includes an array of insulated gate field effect transistors formed at the crossings of a plurality of substantially parallel first conductor tracks which form the transistor gate electrodes and a plurality of substantially parallel strip-shaped surface regions which form the source and drain electrode regions of the transistors. The field effect transistors of the device include a first group of transistors having a first threshold voltage and a second group of transistors having a second threshold voltage different from the first. In order to make a more compact, easily-designed and easily-manufactured circuit, the conductor tracks and the strip-shaped surface regions form a nonuniform array in which the track and surface regions need not all be of the same length. Further efficiencies are achieved by branching the strip-shaped surface regions where appropriate to implement the desired logic combination.read more
Citations
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Patent
Semiconductor Integrated Circuit Device
TL;DR: In this article, a low-voltage control without largely increasing the circuit layout area in a low power consumption structure is presented. But the authors focus on the case of low-speed control, where the region operates on voltages between a power supply voltage and a virtual reference potential.
Patent
Logic cell placement method in computer-aided-customization of universal arrays and resulting integrated circuit
Noto Richard,David C. Smith +1 more
TL;DR: In this paper, an improved automatic placement process for placing logic cells in a universal array is proposed, where unused basic units allocated to a given row are distributed along that row in a manner to reduce wiring congestion.
Patent
Power bus routing for providing noise isolation in gate arrays
TL;DR: In this article, a gate array consisting of n columns of transistor cells with two power busses extending substantially along each column to power the cells is provided, and at least one power strip for increasing current availability to the transistor cells is routed across the transistors substantially perpendicular to the n columns.
Patent
Method for fabricating igfet integrated circuits.
TL;DR: In this article, a rapid and systematic method for performing chip layout of a random-logic IGFET circuit includes steps for arranging the device features and interconnection features corresponding to the circuit in respective positions in an array of intersecting rows and columns.
Patent
Semiconductor integrated circuit device with memory cells connected to a divided sub-word line
TL;DR: A memory array is divided into a plurality of circuit blocks which each include wirings composed of electrically conductive polycrystalline silicon layers and circuit elements that will be operated by signals supplied via the wires as mentioned in this paper.
References
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Patent
Semiconductor integrated circuit with implanted resistor element in polycrystalline silicon layer
TL;DR: In this article, a self-aligned N-channel silicon-gate process is used to make a polycrystalline silicon layer which is also used as a gate for an MOS transistor and as an interconnection overlying field oxide.
Patent
Symmetrical cell layout for static RAM
Vernon G. McKenny,Tsiu Chiu Chan +1 more
TL;DR: In this paper, a symmetrical structural layout for the principal components of each cell in a group of four mutually contiguous cells of an array of memory cells is disclosed, and a common drain supply node is centrally disposed within the group and is coincident with the intersection of first and second mutually perpendicular axes of symmetry.
Patent
Dual injector, floating gate MOS electrically alterable, non-volatile semiconductor memory device
TL;DR: In this paper, a dual injector, floating-gate MOS nonvolatile semiconductor memory device (DIFMOS) has been fabricated, using process specifications and design rules of the same general character previously developed for single-level metal gate CMOS devices.
Journal ArticleDOI
Minimum size ROM structure compatible with silicon-gate E/D MOS LSI
H. Kawagoe,N. Tsuji +1 more
TL;DR: A cascade ratioless circuit configuration is used, which is process compatible with silicon-gate metal-oxide semiconductor (MOS) large-scale integration (LSI) using depletion load MOSTs, which describes a new read-only memory (ROM) with minimum geometry.
Patent
Fabrication of integrated circuits containing enhancement-mode FETs and depletion-mode FETs with two layers of polycrystalline silicon utilizing five basic pattern delineating steps
TL;DR: In this paper, the field isolation regions, the enhancement-mode gate electrodes, and the depletion-mode FET gate electrodes are delineated using five basic, lithographic, pattern-delineating steps.