Patent
Layout designing apparatus for integrated circuit, transistor size determining apparatus, circuit characteristic evaluating method, and transistor size determining method
Masakazu Tanaka,Masahiro Fukui +1 more
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TLDR
In this paper, a transistor size optimization section sets various size candidates for each of the transistors, which constitute the integrated circuit, and then selects an optimum transistor size from the transistor size candidates thus set in accordance with the evaluation results obtained by the circuit characteristic evaluation section.Abstract:
The present invention realizes the optimization of a transistor size with higher precision and in a shorter time, in designing a layout for an integrated circuit. A diffusion sharing estimation section estimates a diffusion-sharing region in the layout of the integrated circuit based on circuit data. A circuit characteristic evaluation section evaluates the characteristics, such as area, delay and power consumption, of the integrated circuit in accordance with the information about the diffusion-sharing region estimated by the diffusion sharing estimation section. A transistor size optimization section sets various size candidates for each of the transistors, which constitute the integrated circuit, provides these size candidates to the diffusion sharing estimation section and the circuit characteristic evaluation section, and then selects an optimum transistor size from the transistor size candidates thus set in accordance with the evaluation results obtained by the circuit characteristic evaluation section. Thus, a transistor size can be determined while taking the diffusion sharing into consideration. In addition, unlike a conventional method, it is no longer necessary to repeatedly re-determine a transistor size and perform a compaction.read more
Citations
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Patent
Dynamic array architecture
TL;DR: In this paper, a linear gate electrode track that extends over both a diffusion region and a non-active region of the substrate is defined to minimize a separation distance between ends of adjacent linear gate electrodes segments within the linear-gated electrode track, while ensuring adequate electrical isolation between the adjacent linear gated electrode segments.
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TILOS: A posynomial programming approach to transistor sizing
John P. Fishburn,A. E. Dunlop +1 more
TL;DR: A new transistor sizing algorithm, which couples synchronous timing analysis with convex optimization techniques, is presented, which shows that any point found to be locally optimal is certain to be globally optimal.
Patent
Transistor sizing system for integrated circuits
TL;DR: In this paper, a method and system for improving the design of an integrated circuit by iteratively analyzing the circuit and improving it with each iteration, until a preselected constraint is met, is presented.
Patent
Method of routing an integrated circuit
TL;DR: In this paper, a linear order of tie styles is determined and ties are placed horizontally in the layout based upon an initial tie style, followed by routing and compact layout components, until the cell satisfies the tie coverage rules.
Patent
Modeling, characterization and simulation of integrated circuit power behavior
TL;DR: In this paper, a method for accurately and efficiently simulating power behavior of digital VLSI MOS circuits at the gate-level is presented, where power consumption is modeled in terms of power-coefficients of the power dissipation model.
Patent
Method and apparatus for optimizing transistor cell layout with integrated transistor folding
TL;DR: In this article, a computer implemented method for generating a layout for a set of transistors on a semiconductor chip is described, which comprises the step of folding transistors of the set whose sizes exceed a predetermined maximum size.