Open AccessProceedings Article
Lightweight mix columns implementation for AES
Eslam Gamal Ahmed,Eman Shaaban,Mohamed Hashem +2 more
- pp 48-53
TLDR
A compact architecture for the AES mix columns operation and its inverse is presented and it is shown that the design has a lower gate count than other designs that implement both the forward and the inverse mix column operation.Abstract:
Since the debut of the Advanced Encryption Standard (AES), it has been thoroughly studied by hardware designers with the goal of reducing the area and delay of the hardware implementation of this cryptosystem. This paper proposes an implementation of the AES mix columns operation. In this paper, a compact architecture for the AES mix columns operation and its inverse is presented. The hardware implementation is compared with previous work done in this area. We show that our design has a lower gate count than other designs that implement both the forward and the inverse mix columns operation.read more
Citations
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Proceedings ArticleDOI
Performance analysis of advanced encryption standard for low power and area applications
T. Manoj Sharma,R. Thilagavathy +1 more
TL;DR: The implementation results of S-Box, MixColumn Transformation and overall AES encryption/ decryption are given and the proposed design was also implemented in 180nm CMOS technology.
Journal ArticleDOI
Design and Implementation A different Architectures of mixcolumn in FPGA
TL;DR: In this article, the implementation of AES under VHDL language in FPGA by using different architecture of mixcolumn is described and evaluated using Altera Cyclone III Family devices.
DissertationDOI
Some aspects of interference minimization, mobile data propagation and data encryption in Wireless Sensor Networks
TL;DR: In this paper, the authors explore certains aspects des reseaux de capteurs without fils, i.e., a set of petits appareils limites en ressources, appeles capteur ou plus simplement nœuds.
Journal ArticleDOI
A full matrix joint optimization method for hardware implementation of AES MixColumns/InvMixColumns
Xiaoqiang Zhang,Xiaoqiang Zhang,Xiaoqiang Zhang,Fan Yang,Fan Yang,Xinxing Zheng,Xinggan Zhang,Ning Wu +7 more
TL;DR: Both analyses results and synthesized results indicate that, compared with column joint optimization and row joint optimization, the optimization efficiency is improved greatly in the whole matrix joint optimization.
References
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Book
Cryptography and Network Security: Principles and Practice
TL;DR: The new edition of William Stallings' Cryptography and Network Security: Principles and Practice, 5e is a practical survey of cryptography and network security with unmatched support for instructors and students.
Journal ArticleDOI
AES implementation on a grain of sand
TL;DR: A hardware implementation of the advanced encryption standard (AES) which is optimised for low-resource requirements and nearly ignorable power consumption in combination with the extreme area efficiency allows new fields of applications for AES which were beyond imagination before.
Journal ArticleDOI
A highly regular and scalable AES hardware architecture
TL;DR: This article presents a highly regular and scalable AES hardware architecture, suited for full-custom as well as for semicustom design flows, that is scalable in terms of throughput and of the used key size.
Proceedings ArticleDOI
An efficient architecture for the AES mix columns operation
Hua Li,Zachary Friggstad +1 more
TL;DR: The design has a lower gate count than other designs that implement both the forward and the inverse mix columns operation and its inverse, and is compared with previous work done in this area.
Proceedings ArticleDOI
A 2.29 Gbits/sec, 56 mW non-pipelined Rijndael AES encryption IC in a 1.8 V, 0.18 /spl mu/m CMOS technology
TL;DR: This paper presents an ASIC implementation of the Rijndael core, which includes a non-pipelined encryption datapath with an on-the-fly key schedule data path.
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