Limitations on HTS single flux quantum logic

TLDR: In this article, the authors studied the effect of layout induced stray inductance on the feasibility of HTS circuits using the T flip-flop as an example and developed numerical methods to study noise induced errors and how they depend on circuit parameters.

Abstract: There is widespread interest in transferring Single Flux Quantum (SFQ) logic from niobium technology to a suitable HTS technology. The higher operating temperature results in increased noise and associated errors. We have developed numerical methods to study noise induced errors and how they depend on circuit parameters. A simple picture holds for all the circuits studied to date. The error probability shows an error function (integrated Gaussian) distribution. The width of the distribution is circuit dependent, but is 1 to 4 times the noise contribution of a single junction, and the noise free (deterministic) margin corresponds to the point where the error probability is 0.5. The distributions are frequently asymmetric, and minimum error rate does not occur for a design centered between the deterministic margins. A stochastic optimizer has been developed that allows us reoptimize circuits for conditions when noise induced margin narrowing is important. We have used this to study the influence of layout induced stray inductance on the feasibility of HTS circuits using the T flip-flop as an example. Stray inductance appears to be as important as junction reproducibility, and significant improvements are needed to allow high operating temperatures.