Proceedings ArticleDOI
Manufacturing challenges and method of fabrication of on-chip capacitive digital isolators
Pushpa Mahalingam,D. Guiling,Sunny K. Lee +2 more
- pp 1-4
Reads0
Chats0
TLDR
In this paper, a robust and innovative method of fabrication of on-chip capacitive digital isolators integrated in a high precision analog CMOS process is presented, where several dielectric materials such as TEOS, HDP, silicon nitride, silicon oxynitride, with different film stresses were evaluated for this capacitor in order to achieve the high breakdown voltage (RMS and surge) requirements of the isolation capacitor while ensuring wafer manufacturability.Abstract:
A robust and innovative method of fabrication of on-chip capacitive digital isolators integrated in a high precision analog CMOS process is presented in this paper Several dielectric materials such as TEOS, HDP, silicon nitride, silicon oxynitride, with different film stresses were evaluated for this capacitor in order to achieve the high breakdown voltage (RMS and surge) requirements of the isolation capacitor while ensuring wafer manufacturability Impact of various integration schemes and combinations of the dielectric layers on the capacitor breakdown voltage performance along with a package and wafer-level reliability assessment of these integration schemes is discussedread more
Citations
More filters
Proceedings ArticleDOI
Highly Integrated Galvanically Isolated Systems for Data/Power Transfer
TL;DR: Main research aims such as the improvement of the isolation rating, data rate, isolated power level and power efficiency, along with the isolator size and cost will be considered.
Proceedings ArticleDOI
A Compact 6 ns Propagation Delay 200 Mbps $100\ \text{kV}/\mu \mathrm{s}$ CMR Capacitively Coupled Direction Configurable 4-Channel Digital Isolator in Standard CMOS
Shi Guangda,Renhui Yan,Jianxiong Xi,Lenian He,Ding Wanxin,Wenjie Pan,Zhenqing Liu,Yang Feng,Chen Dongpo +8 more
TL;DR: A small-size on-chip capacitively coupled 4-channel direction-configurable digital isolator in standard CMOS technology is proposed to achieve high noise immunity and post simulation shows that the proposed architecture achieves 200 Mbps data rate.
Proceedings ArticleDOI
25.4 A 500Mb/s 200pJ/b die-to-die bidirectional link with 24kV surge isolation and 50kV/µs CMR using resonant inductive coupling in 0.18µm CMOS
Subhashish Mukherjee,Anoop Narayan Bhat,Kumar Anurag Shrivastava,Madhulatha Bonu,Benjamin Michael Sutton,Venugopal Gopinathan,Ganesan Thiagarajan,Abhijit Patki,Jhankar Malakar,Nagendra Krishnapura +9 more
TL;DR: An isolation technique is proposed where two standard 180nm CMOS dies placed side by side with DTI of more than 500µm, and co-packaged using regular planar MCM flow with package mold compound being the isolation material, achieve asynchronous bidirectional link with >24kV surge isolation capability and greater than 500Mb/s at 175pJ/b.
Book ChapterDOI
Reinforced Galvanic Isolation: Integrated Approaches to Go Beyond 20-kV Surge Voltage (invited)
TL;DR: Two approaches for data and power transfer are discussed, which exploit the RF coupling between two isolated interfaces, while packaging/assembling techniques are used to guarantee high galvanic isolation.
Journal ArticleDOI
Novel TCAD Approach for the Investigation of Charge Transport in Thick Amorphous SiO 2 Insulators
Federico Giuliano,Susanna Reggiani,Elena Gnani,Antonio Gnudi,Mattia Rossetti,Riccardo Depetro,Giuseppe Croce +6 more
TL;DR: In this article, a TCAD approach for the investigation of charge transport in amorphous silicon dioxide is presented for the first time, where the role of charge injection at contacts and charge build-up due to trapping-detrapping mechanisms in the bulk of the oxide layer has been investigated and modeled to the purpose of understanding the oxide behavior under dc-and ac-stress conditions.
References
More filters
Journal ArticleDOI
Integrated transformer-coupled isolation
TL;DR: The iCoupler technology as mentioned in this paper is a chip-scale transformer technology that minimizes the design burden associated with the use of isolation, and it has been shown to improve the performance of isolation devices.