1
Maximum Circuit Activity Estimation Using
Pseudo-Boolean Satisfiability
Hratch Mangassarian, Student Member, IEEE, Andreas Veneris, Senior Member, IEEE,
and Farid N. Najm, Fellow, IEEE
Abstract—With lower supply voltages, increased integration
densities and higher operating frequencies, power grid verifi-
cation has become a crucial step in the VLSI design cycle. The
accurate estimation of maximum instantaneous power dissipation
aims at finding the worst-case scenario where excessive simul-
taneous switching could impose extreme current demands on
the power grid. This problem is highly input-pattern dependent
and is proven to be NP-hard. In this work, we capitalize on
the compelling advancements in satisfiability solvers to propose
a pseudo-Boolean satisfiability-based framework that reports the
input patterns maximizing circuit activity, and consequently peak
dynamic power, in combinational and sequential circuits. The
proposed framework is enhanced to handle unit gate delays and
output glitches. In order to disallow unrealistic input transitions,
we show how to integrate input constraints in the formulation.
Finally, a number of optimization techniques, such as the use
of gate switching equivalence classes, are described to improve
the scalability of the proposed method. An extensive suite of
experiments on ISCAS85 and ISCAS89 circuits confirms the
robustness of the approach compared to simulation-based tech-
niques and encourages further research for low-power solutions
using Boolean satisfiability.
Index Terms—Maximum Circuit Activity, Peak Dynamic
Power, SAT, Pseudo-Boolean Satisfiability.
I. INTRODUCTION
Lower supply voltages, increased integration densities, and
higher operating frequencies, among other factors, are produc-
ing devices that are more sensitive to power dissipation and
reliability problems [1, 2]. Excessive power dissipation can
lead to overheating, electromigration and a reduced chip life-
time [3]. Also, large instantaneous power consumption causes
voltage drop and ground bounce, resulting in circuit delays and
soft errors [4]. Therefore, accurate power estimation during the
design phase is crucial to avoid a time-consuming redesign
process and in the worst-case an extremely costly tape-out
failure [3]. As a result, reliability analysis has steadily become
a critical part of the design process of digital circuits.
In CMOS circuits, power dissipation depends on the extent
of circuit switching activity, which is input pattern dependent.
Copyright
c
2011 IEEE. Personal use of this material is permitted.
However, permission to use this material for any other purposes must be
obtained from the IEEE by sending an email to pubs-permissions@ieee.org.
H. Mangassarian is with the Department of Electrical and Computer
Engineering, University of Toronto, Toronto, ON, Canada, M5S 3G4
(hratch@eecg.toronto.edu).
A. Veneris is with the Department of Electrical and Computer Engineering
and with the Department of Computer Science, University of Toronto, Toronto,
ON, Canada, M5S 3G4 (veneris@eecg.toronto.edu).
F. N. Najm is with the Department of Electrical and Computer Engineering,
University of Toronto, Toronto, ON, Canada, M5S 3G4 (f.najm@utoronto.ca).
The maximum circuit activity estimation problem aims at
finding the input patterns which cause peak instantaneous
dynamic power: A worst-case scenario where excessive si-
multaneous gate switching imposes extreme current demands
on the power grid [1], leading to unwanted voltage drops.
This problem is NP-complete for combinational circuits, and
PSPACE-complete for sequential circuits [5].
Existing methods for maximum activity estimation can
be classified into the two general categories of simulation-
based and non-simulative approaches [6]. The former rely
on extensive circuit simulations under representative input
vectors. On the other hand, non-simulative approaches use
characteristics of the circuit and stochastic properties of input
vectors to perform power estimation without explicit circuit
simulation [6].
In this work, we leverage the advancements and ongoing
research in satisfiability-based solvers [19, 20, 22] to tackle
this problem using a symbolic approach. Boolean satisfiability
(SAT) solvers and their extensions, such as quantified Boolean
formula satisfiability (QBF) solvers and pseudo-Boolean sat-
isfiability (PBS) solvers, have become attractive tools for
solving theoretically intractable problems in VLSI CAD, in
areas such as testing [21], verification [25] and physical
design [27]. Furthermore, any improvement to the state-of-the-
art in satisfiability solving translates into an immediate benefit
to all satisfiability-based solutions.
A pseudo-Boolean satisfiability-based framework is pre-
sented for generating tight lower bounds on maximum
weighted circuit activity within a clock-cycle [17]. The de-
scribed framework is applicable to both combinational and se-
quential circuits, and to both zero and unit gate delay models.
Glitches are accounted for in the unit gate delay formulation.
As a formal method, our technique may be less scalable than
simulation-based frameworks. For this reason, it is intended
as a complementary, rather than an alternative, approach to
simulations, that can discover “hidden” activity corner-cases.
Additionally, the proposed method is not applicable in the
presence of variability or uncertainty in gate delays.
In order to disallow unrealistic input transitions and invalid
initial states, we show how to integrate input constraints in
the problem formulation. Several optimization techniques are
presented to improve the scalability of the proposed method.
In particular, switching equivalence classes are used to group
gates that are most likely to switch in tandem, thus reducing
the symbolic problem size.
An extensive suite of experiments on ISCAS85 and IS-
CAS89 circuits confirms the effectiveness of SAT in a low-
2
power analysis application. Coupled with the modeling flex-
ibility offered by SAT and its extensions, this encourages
further research in the use of satisfiability-based tools as
platforms to solve other low-power problems.
The paper is organized as follows. Section II summarizes
previous work. Section III presents background on SAT and
PBS. Section IV briefly discusses assumptions and preliminar-
ies. Section V gives the pseudo-Boolean satisfiability formula-
tions for the maximum activity problem in combinational and
sequential circuits. Section VI extends the framework to han-
dle glitches due to gate delays. Section VII describes how to
apply input constraints to disallow unrealistic input transitions.
Section VIII discusses optimizations and heuristics. Section IX
shows experimental results and Section X concludes the paper.
II. PREVIOUS WORK
A number of techniques have been proposed in the literature
to estimate the maximum peak power dissipation [9-15] or
the maximum instantaneous current [4, 7, 8] of a CMOS
circuit. In [4, 7], a loose upper bound on the maximum
instantaneous current is generated in linear time by propagat-
ing signal uncertainties. This bound is subsequently tightened
using a branch-and-bound algorithm that considers spatial
signal correlations. Extending the characterization of signal
correlations from [4, 7] and the authors in [8] exploit mutually
exclusive gate switching to generate tighter upper bounds.
However, for larger circuits, the gap between the generated
upper bounds and lower bounds obtained using simulations
can remain considerable.
In [9], the authors present an Automatic Test Pattern
Generation (ATPG) based greedy algorithm that attempts to
maximize fanout-weighted gate flips. They also provide a
statistical quality measure for the generated lower bounds on
maximum circuit activity. In [10], the method is extended to
cover sequential circuits as well as glitches. A continuous
optimization method is set forward in [11], which treats the
Boolean input space as a real-valued vector space and makes
use of a gradient based heuristic to estimate the maximum
power.
The authors in [12] use genetic algorithms to compare
the effect of different delay models on peak power. They
conclude that peak power estimated using a zero-delay model
is inaccurate, whereas peak power estimated using a unit-delay
model is reasonably accurate. In [13], various genetic spot-
optimization heuristics are employed to avoid local maxima
during the search for maximum single-cycle activities using a
variable delay model. [13] reports significant improvements
over simulations. Both [12] and [13] are able to handle larger
circuits and more general delay models than symbolic ap-
proaches such as ours. However, unlike symbolic techniques,
they are unable to prove the optimality of their results.
The work presented in [14] considers n independent and
identically distributed samples of power-per-cycle. Drawing on
the theory of asymptotic extreme order statistics, they model
the largest of the n sample values using a Weibull distribution.
They then perform a maximum likelihood estimation of the
largest power value. The approach of [6] is an extension
of [14], which handles more corner cases and uses different
statistical distributions. For example, instead of a Weibull-
maxima model, [6] uses the so-called Beta-exceedances model.
Both of these methods are considered simulative approaches,
and are therefore highly input-pattern dependent and lack the
exhaustive property of symbolic techniques. However, they can
handle any delay model and they scale better than symbolic
techniques.
The approach that is closest to this work is given in
[15], where the power dissipation of a circuit is modeled
as a multi-output Boolean function in terms of the primary
inputs. A disjoint cover enumeration as well as a branch-
and-bound algorithm are used to maximize the number of
weighted gate transitions. An approximation strategy for upper
bounding maximum power is also proposed. However, the
described techniques can become computationally expensive.
Furthermore, sequential circuits are not covered.
The work in [16], published after our original paper [17],
proposes the use of temporal and spatial windows in order
to split the original maximum activity estimation problem
into smaller, more manageable subproblems. They present a
high-level algorithm for using symbolic simulation to create
a symbolic network, which is then translated to a pseudo-
Boolean optimization problem. They do not describe the
construction of this symbolic network in detail. The addition of
spatial and temporal restrictions on the optimization problem
in [16] is orthogonal to our work, and provides a viable method
to scale activity estimation techniques, including the approach
described in this paper. It should be noted that our work [17]
was the first to propose such a PBO-based approach to activity
estimation.
III. BACKGROUND
A. Boolean Satisfiability
A propositional logic formula Φ can be constructed over a
set of Boolean variables using Boolean connectives such as
¯(negation), ∧ (conjunction) and ∨ (disjunction). Φ is said to
be satisfiable or SAT if it has a satisfying assignment: a truth
assignment to each of its variables that causes it to evaluate
to 1. Otherwise, Φ is said to be unsatisfiable or UNSAT.
The problem of Boolean satisfiability consists of determining
whether Φ is SAT. In modern SAT solvers, the logic formula Φ
is given in Conjunctive Normal Form (CNF) as a conjunction
of clauses where each clause is a disjunction of literals. A
literal is an instance of a variable or its negation. In order
for a formula to be SAT, at least one literal in each clause
must evaluate to 1. For example, the CNF formula given in
(1) is SAT since {x
1
= 1, x
2
= 0, x
3
= 1} is a satisfying
assignment.
Φ = (x
1
∨ x
2
) ∧ (x
1
∨ ¯x
2
∨ ¯x
3
) ∧ (x
3
) (1)
A logic circuit can be converted to a CNF formula in
linear time under reasonable assumptions [21], such that there
is a one-to-one correspondence between the variables of the
generated CNF formula and the gates of the corresponding cir-
cuit, and such that satisfying variable assignments in the CNF
formula correspond to valid gate output values in the circuit.
3
As such, a circuit and its corresponding SAT formulation are
often referred to interchangeably in this paper.
Modern SAT solvers implement Conflict-Driven Clause
Learning (CDCL) [30]. They are able to solve large industrial
SAT problems with millions of variables and clauses. During
the search, SAT solvers prune parts of the search-space that do
not contain satisfying assignments by analyzing their decisions
and learning conflict clauses. For example, consider the CNF
formula in (1) and suppose that the solver has made the
unsatisfiable variable assignments {x
1
= 0, x
2
= 1, x
3
= 1}.
A conflict is generated and analyzed by the solver, which
realizes that {x
1
= 0} cannot be extended to a satisfying
assignment, and therefore adds the conflict clause (x
1
) to Φ
in order to force {x
1
= 1}.
B. Pseudo-Boolean Satisfiability
A pseudo-Boolean constraint over Boolean variables
x
0
, x
1
, . . . , x
n−1
is an inequality of the form:
n−1
X
i=0
c
i
· l
i
≥ c
n
(2)
where c
i
∈ Z and l
i
is a literal corresponding to x
i
, i.e. l
i
= x
i
or l
i
= ¯x
i
. Note that a CNF clause is a special case of a
pseudo-Boolean constraint with c
i
= 0 or 1, and c
n
= 1. A
pseudo-Boolean constraint becomes satisfied if (2) holds.
A pseudo-Boolean formula Ψ is a conjunction of pseudo-
Boolean constraints. The problem of pseudo-Boolean satisfia-
bility (PBS) questions the existence of a truth assignment to
x
0
, x
1
, . . . , x
n−1
satisfying all the pseudo-Boolean constraints
in Ψ. A pseudo-Boolean optimization (PBO) problem tries to
find a satisfiable assignment to a PBS problem Ψ that also
minimizes a given objective function:
F(x) =
n−1
X
i=0
d
i
· l
i
(3)
where x = hx
0
, . . . , x
n−1
i and d
i
∈ Z.
For example, given Ψ and F as shown in (4) below, both
{x
1
= 1, x
2
= 0, x
3
= 1} and {x
1
= 1, x
2
= 0, x
3
= 0} are
satisfying assignments. However, the former minimizes F.
Ψ = (2x
1
− 3x
2
≥ 1) ∧ (x
1
+ x
2
+ ¯x
3
≥ 1)
F = ¯x
3
− x
1
+ 2¯x
2
(4)
The classical approach for solving combinatorial optimiza-
tion problems, including PBO, has historically been branch-
and-bound [31]. In general, these algorithms are able to prune
the search tree by using estimates on the value of the optimiza-
tion function. [31] gives an overview of branch-and-bound
techniques for PBO. Motivated by recent advances in SAT
solvers, the most effective SAT techniques, including clause
learning, lazy data structures and conflict-driven branching
heuristics, have been extended to PBO [32]. In this work, we
use the PBO solver MINISAT+ [22] which translates pseudo-
Boolean constraints to SAT and runs a state-of-the-art SAT
solver [20] on the produced SAT instance. The latter approach
is particularly suited to problems consisting of mostly SAT
clauses and relatively few pseudo-Boolean constraints [22],
which is the case in this work. Furthermore, any advancements
in SAT solving directly enhances such a strategy.
In MINISAT+, the objective function is minimized using a
linear search. MINISAT+ first runs the SAT solver without
considering F(x) in order to get an initial SAT solution
x
0
, with F(x
0
) = k, where k is the corresponding initial
value of the objective function. The new pseudo-Boolean
constraint F(x) ≤ k − 1 is subsequently added to the original
problem. The SAT solver is then run on the updated CNF
formula and this process is repeated until the problem becomes
UNSAT. The solution corresponding to the last k before the
problem becomes UNSAT is the optimal solution minimizing
the objective function.
IV. ASSUMPTIONS AND PRELIMINARIES
Flip-flop-controlled synchronous digital circuits are consid-
ered. Primary inputs and flip-flop (DFF) outputs can only
switch at the beginning of the clock-cycle. This assumption
is considered valid in related previous work as well.
The dynamic power dissipation of a CMOS circuit during
a clock-cycle can be approximated as follows:
P =
1
2
V
2
dd
m
X
i=1
C
i
· f
i
(5)
where m is the number of circuit gates, C
i
is the capacitive
load on gate g
i
and f
i
is the output transition count of g
i
during a clock-cycle. Under the assumption that the clock
period is sufficiently small, it is sound to interpret (5) as the
instantaneous dynamic power during that clock-cycle [9-15].
In the remainder of this work, the terms circuit activity and
switched capacitance refer to the summation in (5) and are
used interchangeably.
The following notation is used throughout this paper. T
represents a combinational or sequential circuit and G(T )
denotes the set of gates in T excluding primary inputs and
states. Symbol m denotes the number of gates in G(T ).
Symbols x and s are the Boolean vectors respectively denoting
the primary inputs and state elements (DFFs) of a sequential
circuit T . Variables x
i
and s
i
denote the ith primary input and
state element of T . Variable g
i
refers to ith gate in T and can
assume all basic gate types, such as AND, OR, XOR, NOT and
BUFFER.
Circuit unrolling consists of replicating the combinational
component of a sequential design and connecting the next-
state of each time-frame to the current-state of the following
time-frame. As will be described later, this process allows the
PBO solver to reason on the operation of a sequential circuit.
A superscripted variable (e.g. g
j
) denotes the copy of that
variable in the jth copy of the unrolled circuit T . s
0
denotes
the initial-state of T . FANOUTS(g
i
) (FANINS(g
i
)) denotes the
set of fanouts (fanins) of g
i
. Finally, in all the examples, it
is assumed that C
i
= |FANOUTS(g
i
)| for internal gates and
C
i
= 1 for primary output gates.
4
V. ZERO-DELAY MAXIMUM ACTIVITY COMPUTATION
USING PBO
A. Maximum Activity for Combinational Circuits
Under a zero-delay model, each gate transition count f
i
is
a Boolean variable because g
i
can flip at most once per clock-
cycle. Accordingly, the summation in (5) can be rewritten as:
m
X
i=1
C
i
·
g
i
(x
0
) ⊕ g
i
(x
1
)
(6)
where x
0
and x
1
are consecutively applied primary input
vectors and g
i
(x) denotes the steady-state value of gate g
i
given primary input vector x.
y
2
y
1
T
g
4
g
2
g
3
g
1
x
1
x
2
x
3
(a) Zero-delay gate switch-
ing
C
4
= 1
C
3
= 1
C
2
= 1
C
1
= 3
T
1
T
0
g
1
4
x
1
3
g
1
2
g
1
3
x
1
2
x
1
1
g
1
1
x
0
2
x
0
1
g
0
4
g
0
2
N
g
0
1
g
1
1
g
0
2
g
1
2
g
0
3
g
1
3
g
0
4
g
1
4
xor
1
xor
2
xor
3
xor
4
g
0
3
g
0
1
x
0
3
(b) Zero-delay PBO formulation
Fig. 1. Zero-delay PBO formulation for combinational circuits
One needs to find the pair of consecutive primary input
vectors hx
0
∗
, x
1
∗
i maximizing (6). This problem is formulated
as a PBO problem as follows. A new circuit N is constructed
which contains two replicas of the original circuit T , named
T
0
and T
1
. The primary input vector x
0
(x
1
) is applied to T
0
(T
1
). Next, every pair of corresponding gates, g
0
i
in T
0
and
g
1
i
in T
1
, is fed to a new XOR gate, called xor
i
, in N. Clearly,
the output of each xor
i
yields g
i
(x
0
)⊕g
i
(x
1
). Fig. 1(b) shows
the construction of N for the circuit given in Fig. 1(a).
Let CNF(N) denote the translation of N into CNF clauses
(which are also pseudo-Boolean constraints). Clearly, the
solution of the following PBO problem maximizes the value
of (6):
Ψ = CNF(N)
F = −
m
X
i=1
C
i
· xor
i
(7)
Note that only the target function F is not already given
as a set of clauses. The pseudo-Boolean formula Ψ, which
is simply the CNF of N, markedly suits the choice of the
non-native (SAT-based) PBO solver MINISAT+ [22], since the
latter is only left to translate F into CNF.
Example 1 Consider the original circuit T and the cor-
responding construction N shown in Fig. 1. Disregarding
primary input flips, an optimal solution to the associated PBO
problem is hx
0
∗
, x
1
∗
i = hh0, 0, 0i, h1, 1, 1ii, which amounts
to a total switched capacitance of 6 units by flipping all four
gate outputs as shown in Fig. 1(a).
B. Maximum Activity for Sequential Circuits
Let g
i
(s
0
, x) denote the steady-state value of gate g
i
given
initial-state s
0
and primary input vector x. For a sequential
circuit, the transition count f
i
depends on both primary input
transitions and the initial state. Therefore, estimating the peak
power per cycle for sequential circuits is equivalent to finding
a triplet hs
0
∗
, x
0
∗
, x
1
∗
i consisting of an initial state s
0
and
consecutive primary input vectors, x
0
and x
1
, that maximizes
the following summation:
m
X
i=1
C
i
·
g
i
s
0
, x
0
⊕ g
i
s
1
, x
1
(8)
where s
1
denotes the next-state of the circuit.
g
1
D Q
0
s
1
g
2
g
3
g
4
T
x
3
x
2
y
1
x
1
(a) Zero-delay switching
s
0
1
g
1
1
g
0
1
g
0
1
g
1
4
x
0
3
C
4
= 1
C
3
= 1
C
1
= 2
C
2
= 1
T
0
T
1
xor
4
g
0
3
g
1
3
x
0
1
x
1
1
g
1
4
g
1
3
g
1
2
g
0
2
g
1
1
g
0
1
x
0
2
x
1
3
g
0
3
g
0
4
N
x
1
2
g
1
2
g
0
2
g
0
4
xor
3
xor
2
xor
1
(b) Zero-delay PBO formulation
Fig. 2. Zero-delay PBO formulation for sequential circuits
Finding this triplet is formulated as a PBO problem as
follows. First, DFF inputs (outputs) are transformed into
circuit pseudo-outputs (pseudo-inputs). A new circuit N is
constructed which contains two replicas of this full-scanned
circuit. Moreover, the pseudo-outputs of the first time-frame
T
0
are connected to the corresponding pseudo-inputs of the
second time-frame T
1
. This two time-frame iterative logic
array expansion of the original sequential circuit is referred
to as circuit unrolling. Next, similarly to the combinational
case, every pair of corresponding gates, g
0
i
in T
0
and g
1
i
in
T
1
, is fed to a new XOR gate. Clearly, the output of each xor
i
yields g
i
s
0
, x
0
⊕g
i
s
1
, x
1
. Fig. 2(b) shows the construction
of N for the sequential circuit given in Fig. 2(a). Note that in
this example, s
1
1
= g
0
1
.
The resulting PBO problem can be expressed by the set of
equations in (7), using the above description of the circuit N.
Example 2 Consider the circuit T and the corresponding N
shown in Fig. 2. Not counting flips at DFF outputs (s
1
) or
primary inputs, an optimal solution to the PBO problem for
sequential circuits given in this section is hs
0
∗
, x
0
∗
, x
1
∗
i =
hh0i, h0, 0, 0i, h1, 1, 1ii, which amounts to a total switched
capacitance of 5 units as shown in Fig. 2(a). However, this
solution might be suboptimal if gate delays are considered.
Section VI describes how delay is integrated into the PBO
problem.
5
The given problem formulation allows for any initial state
and primary input transitions to be returned in the optimal
solution. In Section VII, we describe how to add constraints
to the PBS problem to disallow certain initial states, as well
as illegal or unlikely combinations of primary inputs.
VI. MODELING DELAY
Different input signal arrival times might cause a gate to
flip several times during one clock-cycle. In fact, glitches
due to gate propagation delays can dominate the maximum
instantaneous power in some cases [10,12]. On the other hand,
empirical results in [12] show that a unit gate delay model
yields reasonably accurate power estimates. This section dis-
cusses the integration of unit gate delay into the problem
formulation. It is also explained how this can be extended
to arbitrary (but fixed) delay using a preprocessing step.
What follows is applicable to sequential circuits with no
combinational loops (sequential loops are obviously allowed),
in order to avoid unstable and metastable signals. In other
terms, the full-scanned version of the sequential circuit is a
Directed Acyclic Graph (DAG). For each DAG node n
i
∈
{x, s, G(T )}, we define its max-level L(n
i
) and min-level l(n
i
)
as follows:
Definition 1
L(n
i
) =
(
max
{n
j
∈FANINS(n
i
)}
L(n
j
) + 1 if n
i
∈ G(T )
0 if n
i
∈ {x, s}
Definition 2
l(n
i
) =
(
min
{n
j
∈FANINS(n
i
)}
l(n
j
) + 1 if n
i
∈ G(T )
0 if n
i
∈ {x, s}
L(g
i
) and l(g
i
) essentially denote the lengths of, respec-
tively, the longest and shortest simple paths to gate g
i
, in
terms of number of gates, starting from a primary input in x
or a pseudo-input in s. Let L = max
g
i
∈G
L(g
i
) designate the
largest max-level in the circuit. Under a unit-delay model, time
t is a discrete variable, meaningful in {0, . . . , L}. Moreover,
the signal arrival time at the output of gate g
i
following a
certain path from a primary input or a DFF is equal to the
length of the traveled path to gate g
i
.
Let G
t
describe the set of all gates whose max-levels and
min-levels bound t inclusively.
Definition 3 G
t
=
g
i
∈ G|l(g
i
) ≤ t ≤ L(g
i
)
If some gate g
i
does not belong to G
t
, then either l(g
i
) > t
or L(g
i
) < t. The former implies that the shortest signal arrival
time from an input or a pseudo-input to a fanin of g
i
takes at
least t time-steps. So g
i
can only flip strictly after time-step t.
Similarly, the latter implies that g
i
can only flip strictly before
time-step t. Therefore, any gate that could potentially flip at
time-step t belongs to G
t
.
Consider a circuit whose gate logic values have stabilized
given initial state s
0
and primary input vector x
0
. In a unit-
delay framework where each gate requires one time-step to
switch, this is equivalent to applying s
0
and x
0
at t = −1. The
primary input vector x
1
is applied at the start of a new clock-
cycle at t = 0, and we let g
t
i
(s
0
, x
0
, x
1
) denote the value of
gate g
i
at time-step t. Note that the output value of g
i
depends
on both x
0
and x
1
because if t < l(g
i
), g
t
i
(s
0
, x
0
, x
1
) =
g
i
(s
0
, x
0
), which is defined in Section V-B. Accordingly, the
total switched capacitance can be given by:
L
X
t=1
X
g
i
∈G
t
C
i
·
g
t−1
i
(s
0
, x
0
, x
1
) ⊕ g
t
i
(s
0
, x
0
, x
1
)
(9)
The inner summation in (9) adds the capacitances of the
gates whose outputs flip at time t. This summation only
checks gates in G
t
and disregards all other gates, because only
the gates in G
t
can potentially flip at time-step t. The outer
summation adds the total switched capacitances across time-
steps t = 1 to L.
To maximize (9), we will again construct a new circuit N
that will be used by the PBO solver. In order to do so, we need
to create an XOR gate for each term in the summation of (9),
representing each potential glitch. As such, we need to store
the value of each gate at only time-steps when its output value
may potentially flip. The remainder of this section describes
and proves the correctness of a circuit construction N that
“remembers” all gate flips in T .
This construction is illustrated with the use of an example.
Consider the sequential circuit T shown in Fig. 2(a). First, DFF
inputs (outputs) are transformed into circuit pseudo-outputs
(pseudo-inputs). The min-level and max-level of each node can
be calculated in linear time by visiting nodes in topological
order starting from primary inputs and pseudo-inputs. As a
result, the sets G
1
, G
2
, . . . , G
L
can be generated. For the circuit
in Fig. 2(a), these sets are as follows:
G
1
= {g
1
, g
2
, g
4
}, G
2
= {g
2
, g
3
, g
4
},
G
3
= {g
3
, g
4
}, G
4
= {g
4
}.
For each time-step t, for 0 ≤ t ≤ L, we associate a time-
circuit T
t
containing the following time-gates:
G(T
t
) =
(
g
t
i
|g
i
∈ G
t
if t ≥ 1
g
0
i
|g
i
∈ G(T )
if t = 0,
(10)
as shown in Fig. 3. At the base case, T
0
contains all the
gates in T , whereas T
t
, for t ≥ 1, contains every gate that
can potentially switch at time t. The new circuit N in Fig. 3
accommodates all these time-circuits T
0
, T
1
, . . . , T
L
.
Now we describe the gate interconnections in N. The
gates of T
0
are interconnected identically to the original full-
scanned circuit, given pseudo-input vector s
0
and primary
input vector x
0
, as shown in Fig. 3. For a time-gate g
t
i
in time-
circuit T
t
, with t ≥ 1, there are three cases for connecting it to
its new inputs, depending on each fanin of the corresponding
gate g
i
in the original circuit T :
1) If the fanin gate was originally another internal gate, the
given time-gate must be connected to the most recent
corresponding time-gate strictly before the current time-
step: No two time-gates in the same time-circuit can be
connected because they can only change simultaneously.
