Patent
Method of forming a transistor
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TLDR
In this article, the authors proposed a method for forming a double polysilicon self-aligned bipolar transistor using a single masking step for defining the emitter structure with a narrow emitter-base contact area and a large emitter contact area.Abstract:
A method is provided for forming a transistor for a bipolar, CMOS, or bipolar CMOS integrated circuit. The method is applicable to forming a double polysilicon self-aligned bipolar transistor using a single masking step for defining the emitter structure with a narrow emitter-base contact area and a large emitter contact area. The method comprises selectively providing a tapered body of dielectric to mask a region of the substrate on which an emitter is to be formed. A conductive layer is provided around the tapered body to form base contact electrodes. The tapered body is selectively removed from the substrate without damaging the underlying silicon substrate, to leave a tapered opening; localized dielectric isolation is provided in the form of sidewall spacers on the first conductive layer. The tapered opening is filled with a layer of a second conductive material to form a second electrode i.e. an emitter structure. The resulting structure is fully planarized, preferably by chemical mechanical polishing, to form coplanar contact areas to the base and emitter.read more
Citations
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References
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Patent
Lift-off process for fabricating self-aligned contacts
TL;DR: In this article, a process for fabricating self-aligned contacts to the surface of an integrated circuit is described, which includes the steps of depositing a layer of silicon dioxide 12 on the surfaces of a semiconductor structure, defining openings 23 in the polyimide material 15 and the silicon dioxide 6 to expose regions of the semiconductor topology, and depositing metal 22 across the underlying surface and in the openings 23.
Patent
Method of forming t-gate structure on microelectronic device substrate
TL;DR: In this article, a T-gate structure (28a) is fabricated on a microelectronic device substrate (10) using a trilevel resist system in combination with a two-step reactive ion etching (RIE) technique utilizing an oxygen plasma.
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Manufacture of semiconductor device
TL;DR: In this paper, the surface of a semiconductor substrate consisting of some one of laminated wafers is shaved off so as to leave a necessary thickness at the bonding part of the substrate with an intrinsic base and a single crystal is buried in a hole formed by anisotropic etching.
Proceedings ArticleDOI
A sub-30 psec Si bipolar LSI technology
TL;DR: In this article, an extremely high-speed bipolar LSI technology using 0.8- mu m-rule polysilicon emitter-base selfaligned, shallow-junction, and trench-isolation technologies is described.
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Method for forming self-aligned emitters and bases and source/drains in an integrated circuit
TL;DR: In this article, a method for forming a BICMOS device having MOS devices and bipolar devices formed during the same process includes the step of first forming bipolar MOS regions and then forming gate electrodes and poly emitters in the bipolar regions.