Patent
Method of manufacturing an integrated edge structure for high voltage semiconductor devices, and related integrated edge structure
TLDR
In this paper, a method of manufacturing an edge structure for a high voltage semiconductor device, including a first step of forming a first semiconductor layer of a first conductivity type, a second step of formulating a first mask over the top surface of the first semiconducting layer, a third step of removing portions of the mask in order to form at least one opening in it, a fourth step of introducing dopant of a second conductivities type in the first and second semiconductors through the opening, a fifth step of completely removing the first mask and of formingAbstract:
Method of manufacturing an edge structure for a high voltage semiconductor device, including a first step of forming a first semiconductor layer of a first conductivity type, a second step of forming a first mask over the top surface of the first semiconductor layer, a third step of removing portions of the first mask in order to form at least one opening in it, a fourth step of introducing dopant of a second conductivity type in the first semiconductor layer through the at least one opening, a fifth step of completely removing the first mask and of forming a second semiconductor layer of the first conductivity type over the first semiconductor layer, a sixth step of diffusing the dopant implanted in the first semiconductor layer in order to form a doped region of the second conductivity type in the first and second semiconductor layers. The second step up to the sixth step are repeated at least one time in order to form a final edge structure including a number of superimposed semiconductor layers of the first conductivity type and at least two columns of doped regions of the second conductivity type, the columns being inserted in the number of superimposed semiconductor layers and formed by superimposition of the doped regions subsequently implanted through the mask openings, the column near the high voltage semiconductor device being deeper than the column farther from the high voltage semiconductor device.read more
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References
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Patent
Inverted dielectric isolation process
TL;DR: In this article, the authors describe a method of semiconductor fabrication which includes the steps of forming a dielectric layer on a first surface of a semiconductor wafer having a plurality of laterally distributed semiconductor devices selectively interconnected on the first surface and bonding a support substrate to the first surfaces of the semiconductor Wafer on the dielectrics layer to form a composite structure.
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