Proceedings ArticleDOI
Methods for Generalized Deductive Fault Simulation
N. Giambiasi,A. Miara,D. Muriach +2 more
- pp 386-392
TLDR
Methods for generalized deductive fault simulation of digital networks are described by introducing the notion of unknown fault list, and the propagation algorithm through gates modelized with rise and fall times are simplified with the same accuracy.Abstract:
In this paper, the authors describe methods for generalized deductive fault simulation of digital networks. By introducing the notion of unknown fault list, the propagation algorithm through gates modelized with rise and fall times are simplified with the same accuracy.read more
Citations
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Proceedings ArticleDOI
High level hierarchical fault simulation techniques
TL;DR: Techniques for simulating directly from a hierarchical circuit description without flattening to the level of primitives are presented, indicating that hierarchical fault simulation is superior to traditional techniques.
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Expert System Based on Multi-View/Multi-Level Model Approach for Test Pattern Generation
TL;DR: In the first section of this chapter, the author deals with a general structure for model, which can be summarized as consisting of different model views, each view being represented at a number of distinct levels of abstraction.
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A Functional Partitioning Expert System for Test Sequences Generation
TL;DR: This paper describes at first an open infrastructure that allows the integration of specific tools in a hierarchical description of technical systems, being the first step towards test generation at board level.
References
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Journal ArticleDOI
A Deductive Method for Simulating Faults in Logic Circuits
TL;DR: A deductive method of fault simulation is described, which "deduces" the faults defected by a test at the same time that it simulates explicitly only the good behavior of logic circuit.
Journal ArticleDOI
Modeling and Digital Simulation for Design Verification and Diagnosis
TL;DR: This paper will be oriented towards modeling and implementation questions which arise when one is attempting to implement an extremely accurate digital simulator for the purposes of logic and design verification and fault simulation.
Proceedings ArticleDOI
An accurate time delay model for large digital network simulation
TL;DR: A three valued model is proposed for temporal simulation of logic system that is well suited for analysis of hazards and high frequency rejection phenomenas and allows very simple implementation.
Proceedings ArticleDOI
SILOG: A Practical Tool for Large Digital Network Simulation
N. Giambiasi,A. Miara,D. Muriach +2 more
TL;DR: A set of simulators for complex logical networks for developing user facilities and a briefly description of the simulators are presented.