Patent
Methods of forming field effect transistors; methods of forming DRAM circuitry
Fernando Gonzalez,Chandra Mouli +1 more
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TLDR
In this article, the authors provide methods of forming field effect transistors (FETs) that include at least partially forming a patterned transistor gate stack, at least partially defining a channel region therebeneath, and at least partial forming source/drain regions operably adjacent the gate stack and the channel region.Abstract:
Embodiments of the present invention provide methods of forming field effect transistors (FETs) that include at least partially forming a patterned transistor gate stack, at least partially defining a channel region therebeneath, and at least partially forming source/drain regions operably adjacent the gate stack and the channel region. Such embodiments include conducting one or more ion implantations through the at least partially formed gate stack and the at least partially formed source/drain regions to appropriately form Vt adjust regions within the channel regions and minority carrier barrier regions below formed, or to be formed, source/drain regions. Some embodiments of the present invention encompass forming such regions for memory FETs employed in DRAM or other memory circuitry.read more
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References
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Patent
Method of implanting silicon through a polysilicon gate for punchthrough control of a semiconductor device
Mark I. Gardner,Derick J. Wristers,Robert Dawson,H. Jim Fulford,Frederick N. Hause,Mark W. Michael,Bradley T. Moore +6 more
TL;DR: In this paper, a region of damaged silicon is exploited as a gettering region for gettering impurities in a silicon substrate by implanting silicon atoms into the silicon substrate after the formation of a gate electrode of the device.
Patent
Simplified semiconductor device manufacturing using low energy high tilt angle and high energy post-gate ion implantation (PoGI)
TL;DR: In this article, a method for fabrication of a circuit on a substrate is described, where the source/drain extensions are implanted at low energy and at a high tilt angle with respect to a normal to the substrate surface, so that the source and drain extensions are formed laterally under the sidewall spacers.
Patent
MOSFET device structure three spaced-apart deep boron implanted channel regions aligned with gate electrode of NMOSFET device
TL;DR: In this article, a polysilicon spacer is formed on the edges of the gate electrode forming a gate structure with a cavity, and a fully overlapped Lightly-Doped-Drain structure is used to improve device characteristics.
Patent
Multiple threshold voltage semiconductor device fabrication technology
Zoran Krivokapic,Ognjen Milic +1 more
TL;DR: In this article, an integrated circuit process technology for simultaneously forming multiple threshold voltage devices is disclosed, which can be fabricated for use in integrated circuits having a need for both high speed and low power consumption.