Multi-objective optimization ofMOSFETs
channel widths andsupply voltage inthe
proposed dual edge-triggered static D ip-op
withminimum average power anddelay
byusing fuzzy non-dominated sorting genetic
algorithm-II
Farshid Keivanian
*
, Nasser Mehrshad and Abolfazl Bijari
Background
e layout of an electronics circuit plays an important role in the design and usability of
many products (Mihajlovic etal.
2007). In computers, communications, and many other
systems, the flip-flops are fundamental building blocks. ey are the important timing
elements in digital circuits which have great impacts over power consumption and speed.
e performance of Flip-Flop influence the performance of whole synchronous circuit,
Abstract
Background: D Flip-Flop as a digital circuit can be used as a timing element in many
sophisticated circuits. Therefore the optimum performance with the lowest power
consumption and acceptable delay time will be critical issue in electronics circuits.
Findings: The newly proposed Dual-Edge Triggered Static D Flip-Flop circuit layout is
defined as a multi-objective optimization problem. For this, an optimum fuzzy infer-
ence system with fuzzy rules is proposed to enhance the performance and conver-
gence of non-dominated sorting Genetic Algorithm-II by adaptive control of the explo-
ration and exploitation parameters. By using proposed Fuzzy NSGA-II algorithm, the
more optimum values for MOSFET channel widths and power supply are discovered in
search space than ordinary NSGA types. What is more, the design parameters involv-
ing NMOS and PMOS channel widths and power supply voltage and the performance
parameters including average power consumption and propagation delay time are
linked. To do this, the required mathematical backgrounds are presented in this study.
Conclusion: The optimum values for the design parameters of MOSFETs channel
widths and power supply are discovered. Based on them the power delay product
quantity (PDP) is 6.32 PJ at 125 MHz Clock Frequency, L = 0.18 µm, and T = 27 °C.
Keywords: Optimum MOSFETs channel widths and power supply, Proposed Dual
Edge-Triggered Static D Flip-Flop, Minimization of average power and delay, Power
delay product, Fuzzy NSGA-II
Open Access
© 2016 The Author(s). This article is distributed under the terms of the Creative Commons Attribution 4.0 International License
(
http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium,
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TECHNICAL NOTE
Keivanian
et al. SpringerPlus (2016) 5:1391
DOI 10.1186/s40064-016-2987-6
*Correspondence:
Info@keivanian.com;
FarshidKeivanian@Birjand.
ac.ir
Department of Electrical
and Computer Engineering,
University of Birjand, Birjand,
Iran
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Keivanian
et al. SpringerPlus (2016) 5:1391
particularly in deep pipelined design (Bhargavaram and Pillai
2012). In this study, D Flip-
Flop is considered. e optimum layout design of D Flip-Flop can be defined as an opti
-
mization problem. at is solved by the Multi-objective Evolutionary Algorithm (MOEA).
MOEAs are well-suited for solving several complex multi-objective problems with two or
three objectives (Lücken etal.
2014). As the performance of most MOEAs for problems
with four or more conflicting objectives is severely deteriorated (Lücken etal.
2014), for
this study, we define two conflicting objectives. Here we use a multi-objective evolution
-
ary algorithm based on Genetic Algorithm. e non-dominated sorting genetic algorithm-
II, NSGA-II, has questionable exploratory capability (Coello Coello etal.
2007). ere are
three evolutionary processes such as mutation, crossover, and selection. e mutation
operator is used to increase the diversity of off-springs or generated solutions which is
inspired by genetic diversity from one generation of population chromosomes to the next.
e crossover which is inspired by genetic inheritance in parent children is applied to vary
the situation or features of a chromosome or chromosomes from one generation to the
next. e selection procedure is done to select the better or more optimum solutions.
In this study, for the proposed problem we will define two objective functions such as
average power consumption and propagation delay time. ey are minimized by pro
-
posed FNSGA-II when its three operators are implemented. For multi-objective opti-
mization we are looking for the series of non-dominated solutions that are placed in the
category of Pareto Front. ere will not be any other solution better than non-domi
-
nated solutions and no solution will dominate them. e solutions of Pareto Front are
ranked as the first Front F1 since they are the closest Front to the ideal solution in com
-
parison with the other solutions (Coello Coello etal.
2007).
In sequential circuits there are many Flip-Flops. Since changes in the data inputs of a
gated D latch flip-flop have no effect unless the clock is asserted, the propagation delay
is not considered when the data inputs are entered (Mohanram
2014). In combinational
logic circuits the basic blocks are the gates while in sequential logic circuits the flip flops
are principal building blocks. Flip-Flops are clock based devices. Each flip flop can store
one bit. D Flip Flop is the best choice in Integrated Circuit design works (Elias
2014).
e D flip-flop is also known as a “data” or “delay” flip-flop. It captures the value of the
D-input at a definite portion of the clock cycle and then the captured value becomes out
-
put Q. e D flip–flip is one of the most common types of flip-flops. Like all Flip Flops,
it has the ability to retain one bit of digital information. D flip-flop is applicable for syn
-
chronous circuits. In this paper NSGA, NSGA-II, and proposed FNSGA-II are employed
to find the best channel widths and supply voltage in which the D Flip-Flop has the low
-
est average power and propagation delay of proposed dual edge-triggered static D flip-
flop circuit. is study is the further research of the previous article which was the single
objective optimization of JK Flip-Flop layout sizes based on single objective optimiza
-
tion algorithms such as Ant Colony Optimization in Real or continuous domain ACOR,
Fuzzy-ACOR, Genetic Algorithm GA, and Fuzzy-GA in which one objective function,
the average power, was considered for minimization (Keivanian etal.
2014a).
Proposed dual-edge triggered D ip-op
e proposed dual-edge triggered static D Flip-Flop is shown in Fig.
1.
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Overall, the operation of the circuit is to select input DATA and pass it on the output
channel, Q. As it is illustrated in Fig.
1, the circuit is a synchronous multiplexer that can
transmit multiple data simultaneously to output Q based on both edges of CLOCK pulse.
In close view, to analyse the performance of circuit, two NMOSs of M17 and M18 were
connected to each inverter module (one is M13 and M14, the other is M15 and M16) in
order to boost their outputs. Back to back connected inverters keep the data when trans
-
mission gate is off. At the same time multiplexer transmits this latched data to the inverter
to pass the correct DATA on the output line Q. Based on Fig.
1, when the CLOCK is low the
MOSFETs M3, M4 and M18 are all on while M5, M6 and M17 are all off. Hence DATA is
hold by negative latch and is passed to output line Q. In contrast, whenever CLOCK is high
then the MOSFETs M5, M6 and M17 will be on but the MOSFETs M3, M4 and M18 will be
off. In this state, DATA is passed on the output channel Q. So that, in dual edge-triggered D
flip-flip DATA is put forward to output through both low and high states of CLOCK. Before
the next CLOCK, if DATA alters this new amount of DATA is held by positive edge latch
data PELD part and whenever next CLOCK comes and changes from Low to High this
DATA is conveyed to the output channel Q. On the contrary, before the following CLOCK,
if DATA changes this new DATA is hold by Negative Edge Latch Data NELD part and once
next CLOCK arrives and alters from High to Low the DATA reach to the output channel
Q. Without using M19, M20, M21, M22, M23, and M24 the output does not reach to the
standard value of high or low level and there will be some transient time states for output
signals. ey should be a series of standard pulses since the input data is in fact a series of
standard pulses.
e general configuration of multiplexer is shown as the block diagram in Fig. 2
(Nedovic etal.
2002).
Both positive and negative edges are used to sample the DATA at both edges of
CLOCK and the appropriate sample is selected for the output Q by a clocked multi
-
plexer, MUX. By using the double edge clocking the power in the CLOCK distribu-
tion network is saved. Base on Fig.
2, data is captured or sampled by both edges of the
CLOCK also the appropriate sample is selected for the Q output (Singh and Sulochana
2013). In this architecture, the Multiplexer is designed by using two NMOS transistors
Fig. 1 Proposed dual edge-triggered D flip-flop
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as pass transistors that select either the positive edge or negative edge latched data to
pass it to output channel based on Fig.
3 (Keivanian etal. 2014b).
We have proposed a new architecture in this literature that is dual edge-triggered Flip-
Flop with NMOS pass-transistors as Multiplexer. In which the DATA can be passed by
both positive and negative edges of CLOCK. is is more efficient in term of speed com
-
pared with single edge triggered Flip-Flop where DATA can only pass to output channel
in a single triggering state of CLOCK (Singh and Sulochana
2013). In study, the design
and performance parameters of Dual Edge-Triggered D Flip-Flop circuit to define it as
an optimization problem are defined as in Table
1.
In this article all the channel lengths are set as the fixed value and equal to 0.18 micron
L=0.18µm, whereas the channel widths are defined as the design parameters in circuit
layout design literature and as the decision variables in meta-heuristic based optimiza
-
tion algorithms’ literature.
Single-objective optimization
e minimization of average power Pavg (w) is addressed to single objective optimiza-
tion problem and many techniques are demonstrated in this literature (Keivanian etal.
2014a, b; Keivanian 2014). For example, for single objective optimization of JK flip flop
Fig. 3 The 2:1 multiplexer with NMOS pass-transistor
Table 1 The design andperformance parameters ofdual edge-triggered D ip-op inthis
article
Design parameters Performance parameters
Supply voltage (V
DD
) Total average power (P
t
)
PMOS channel width (W
PMOS
)
NMOS channel width (W
NMOS
) Propagation delay time (t
PD
)
Fig. 2 Dual-edge-triggered flip flops
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layout sizes the least dynamic average power obtained was 1.6nw. But the propagation
delay was not considered for optimization as a result the layout sizes could not provide
the optimum speed for the circuit. is encouraged us to study more on the multi-objec
-
tive optimization algorithms and the design and performance parameters of proposed
dual edge-triggered static D flip-flop circuit in order to minimize its dynamic average
power dissipation and propagation delay.
Multi-objective optimization
Although single-objective optimization problems may have a unique optimal solution,
multi-objective optimization problems, MOPs present a possible uncountable set of
solutions, which when evaluated, produce vectors whose components represent trade-
offs in objective space. Here the objective space is two dimensional including power con
-
sumption and delay objectives. In multi-objective optimization area a decision maker
finally chooses an acceptable solution or solutions by selecting one or more of the solu
-
tions (Coello Coello etal.
2007). In this research work, the decision maker in fact is the
electronic designers who evaluate the conditions and choose a candidate solution from
the obtained set of solutions that it will have a minimum power delay product value.
e vector of decision variables in the Multi-objective optimization problem is found
and satisfies the constraints and optimizes the objective functions (Coello Coello etal.
2007). ese functions form a mathematical description of performance of problem
which are usually in conflict with each other. In this article there is conflict between
propagation delay and dynamic power dissipation (Singh and Sulochana
2013). e
design parameters of problem are discovered to find optimum power consumption with
reasonable delay time. So both will not be ideally obtained and a trade-off between them
is required. Hence, the term “optimizes” means finding such a solution which would give
the values of all the objective functions acceptable to the decision maker (Coello Coello
etal.
2007).
In this article, our goal is to achieve a candidate solution for layout sizes and power
supply values of circuit that will lead to a circuit with 6.32PJ power delay product. So we
firstly try to obtain optimum set of solutions with good performance then select a candi
-
date solution from them with PDP=6.32PJ.
Decision variables
e decision variables are the numerical quantities or control parameters of an optimi-
zation problem. In this article these quantities are denoted as x
i
, i=1, 2, 3. T stands for
transpose. en the vector x with 3 decision variables is represented by the relation (
1):
Constraints
In most optimization problems some restrictions are proposed because of particu-
lar characteristics or physical limitations. In this study, the channel length is selected
smaller than the channel width based on the relations (2) and (3). If the channel length
L is selected as larger value of the channel width W, any change in W along the channel
(1)
X
T
=
[
V
DD
W
PMOS
W
NMOS
]