Journal ArticleDOI
Modeling and optimized design of current mode MUX/XOR and D flip-flop
Massimo Alioto,Gaetano Palumbo +1 more
Reads0
Chats0
TLDR
Current mode logic and models and optimized design strategies for MUX, XOR, and D flip-flop are presented, providing a better insight into the relationship between delay and its electrical parameters, which in turn are related to process parameters.Abstract:
This paper deals with current mode logic (CML) and, in particular, models and optimized design strategies for MUX, XOR, and D flip-flop are presented. Both simple and accurate models for propagation delay are proposed. The models represent propagation delay with a few terms, providing a better insight into the relationship between delay and its electrical parameters, which in turn are related to process parameters. The main difference between accurate and simple models is that the former need only a few SPICE simulations to properly evaluate model parameters. The simple models show errors which are always lower than 20%, while accurate models have typical errors of 2%. Design optimization is in terms of bias currents giving minimum propagation delay, and it has been demonstrated that at the cost of a 10% increase in propagation delay we can reduce power dissipation by 40%. The models and design strategies are validated using both a traditional and a high-speed bipolar process which have a transition frequency equal to 6 and 20 GHz, respectively.read more
Citations
More filters
Proceedings ArticleDOI
A CMOS impulse generator for UWB wireless communication systems
TL;DR: A fully integrated CMOS impulse generator was designed as a part of the System-on-Chip (SOC) implementation of an Ultra-Wide-Bandwidth (UWB) wireless communication system to avoid using off-chip components.
Journal ArticleDOI
2.5 V 43–45 Gb/s CDR Circuit and 55 Gb/s PRBS Generator in SiGe Using a Low-Voltage Logic Family
D. Kucharski,Kevin Kornegay +1 more
TL;DR: In this article, an alternative design approach for implementing high-speed digital and mixed-signal circuits is proposed based on a family of low-voltage logic gates with reduced transistor stacking compared to series-gated emitter-coupled logic.
Journal ArticleDOI
Performance evaluation of the low-voltage CML D-latch topology
TL;DR: Analysis shows that the low-voltage D-latch topology does not necessarily allow for a power saving or a better power efficiency, and applications where this topology exhibits some advantage over the traditional implementation are identified.
Journal ArticleDOI
Up-to-Date Bibliography of Current-Mode Design
Proceedings ArticleDOI
A 4-54GHz Static Frequency Divider with Back-Gate Coupling
Jung-Yu Chang,Shen-Iuan Liu +1 more
TL;DR: In this article, a static frequency divider by using the back-gate coupling technique is presented, and the measured operating frequency range of the conventional circuit is from 4 GHz to 48 GHz, while that of the proposed circuit was from 4GHz to 54 GHz by choosing the same device size.
References
More filters
Book
Analysis and Design of Analog Integrated Circuits
Paul R. Gray,Robert G. Meyer +1 more
TL;DR: In this article, the authors combine bipolar, CMOS and BiCMOS analog integrated circuits into a unified treatment that stresses their commonalities and highlights their differences, and provide valuable insights into the relative strengths and weaknesses of these important technologies.
Book
Digital integrated circuits: a design perspective
TL;DR: In this paper, the authors present a survey of the state-of-the-art in the field of digital integrated circuits, focusing on the following: 1. A Historical Perspective. 2. A CIRCUIT PERSPECTIVE.
Journal ArticleDOI
Design considerations for very-high-speed Si-bipolar IC's operating up to 50 Gb/s
Hans-Martin Rein,M. Moller +1 more
TL;DR: In this paper, design aspects of high-speed digital and analog IC's are discussed which allow the designer to exhaust the high speed potential of advanced Si-bipolar technologies, starting from the most promising circuit concepts and an adequate resistance level, the dimensions of individual transistors in the IC's must be optimized very carefully using advanced transistor models.
Journal ArticleDOI
Bipolar transistor design for optimized power-delay logic circuits
D.D. Tang,P.M. Solomon +1 more
TL;DR: In this article, the impurity doping profile of the transistor was optimized to optimize the performance of the logic circuit at a specific power dissipation level and a given lithographic line width.
Journal ArticleDOI
Accurate analytical delay expressions for ECL and CML circuits and their applications to optimizing high-speed bipolar circuits
TL;DR: In this article, a linearity study of the propagation delay of bipolar circuits carried out using a SPICE program is discussed, and therefore analytical propagation delay expressions for ECL and CML circuits are derived using a sensitivity analysis.
Related Papers (5)
Design techniques for low-voltage high-speed digital bipolar circuits
Behzad Razavi,Y. Ota,R.G. Swartz +2 more