Patent
Multi-voltage compatible bidirectional buffer
TLDR
In this paper, an integrated circuit is disclosed comprising a first field effect transistor having a source connected to a first node and a gate connected to the second node, and a second field-effect transistor for protecting the first transistor from voltages that are greater than a predetermined nominal voltage.Abstract:
An integrated circuit is disclosed comprising a first field effect transistor having a source connected to a first node and a gate connected to a second node, and a second field effect transistor for protecting the first transistor from voltages applied to the first node and greater than a predetermined nominal voltage. The second transistor includes a drain connected to the second node, a source connected to the first node, and a gate connected to a third node. A constant voltage source is coupled to the third node and supplies a gate voltage to the gate of the second transistor such that a drain-source path of the second transistor does not conduct while voltage applied to the first node is generally less than the gate voltage plus a threshold voltage of the second transistor. The constant voltage source comprises a third field effect transistor having a drain and a gate connected to the third node, and a source coupled to a first power supply voltage, such that the gate voltage is substantially equal to the first power supply voltage minus a threshold voltage of the third transistor.read more
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Patent
Output buffer with improved tolerance to overvoltage
Hamid Partovi,Matthew P. Crowley +1 more
TL;DR: In this paper, an output buffer with improved tolerance to overvoltage conditions was proposed, where the output buffer prevents a leakage path from a pad through a pull-up driver to supply voltage VDD when any voltage above VDD is placed on the pad.
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Overvoltage-tolerant interface for integrated circuits
TL;DR: In this paper, an input/output driver for interfacing directly with a voltage at a pad (820) which is above a supply voltage (817) for the driver is described.
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Low voltage interface circuit with a high voltage tolerance
TL;DR: In this article, a tri-state control circuit, a data path, a reference voltage circuit, and an isolation circuit are presented for low-voltage interfaces with high voltage tolerance.
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TL;DR: In this article, the authors present a model where the level of a resistance value of one of the first and second switching elements is set to a predetermined level, to the elements via shared signal wire.
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Integrated circuit I/O buffer with 5V well and passive gate voltage
TL;DR: In this article, a pull-up voltage protection transistor is coupled in series between the pad pull-down transistor and the pad terminal and has a control terminal which is coupled to the pad terminals through a voltage feedback circuit.
References
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Patent
Voltage compensating CMOS input buffer
TL;DR: The CMOS voltage compensating input buffer circuit of as mentioned in this paper provides a means to stabilize input level trip points and is comprised of a voltage compensated circuit having an input node and an output drive node coupled to an input buffer.
Patent
Voltage interfacing buffer with isolation transistors used for overvoltage protection
TL;DR: In this paper, the authors proposed a voltage interfacing buffer for interfacing a low voltage integrated circuit to a high voltage environment, wherein the integrated circuit contains only low voltage transistors.
Patent
Low-voltage CMOS output buffer
TL;DR: In this article, the P-channel pull-up transistor (11) of a push-pull output buffer was used to resist the voltage elevation of the output node to higher voltage without sinking large currents into the low-voltage supply.
Proceedings ArticleDOI
3.3V-5V compatible I/O circuit without thick gate oxide
TL;DR: A novel 3.3V-5V compatible [/O circuit is proposed and measured to be effective from the stand-point of reliability and speed and can endure 5V input from the external chips.
Patent
Non-loading output driver circuit
TL;DR: In this paper, an output driver for an IC (14, 16 and 18) to drive a data bus (12) connected to the IC is described; the output driver may include a push-pull configuration comprising both a P and N channel transistor (78 and 80, respectively).