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NaNet: a flexible and configurable low-latency NIC for real-time trigger systems based on GPUs

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TLDR
NaNet is an FPGA-based PCIe X8 Gen2 NIC supporting 1/10 GbE links and the custom 34 Gbps APElink channel, making it suitable for building low-latency, real-time GPU-based computing systems.
Abstract
NaNet is an FPGA-based PCIe X8 Gen2 NIC supporting 1/10 GbE links and the custom 34 Gbps APElink channel. The design has GPUDirect RDMA capabilities and features a network stack protocol offloading module, making it suitable for building low-latency, real-time GPU-based computing systems. We provide a detailed description of the NaNet hardware modular architecture. Benchmarks for latency and bandwidth for GbE and APElink channels are presented, followed by a performance analysis on the case study of the GPU-based low level trigger for the RICH detector in the NA62 CERN experiment, using either the NaNet GbE and APElink channels. Finally, we give an outline of project future activities.

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Proceedings ArticleDOI

Lynx: A SmartNIC-driven Accelerator-centric Architecture for Network Servers

TL;DR: Lynx is proposed, an accelerator-centric network server architecture that offloads the server data and control planes to the SmartNIC, and enables direct networking from accelerators via a lightweight hardware-friendly I/O mechanism, which enables the design of hardware-accelerated network servers that run without CPU involvement.
Journal ArticleDOI

NaNet: a configurable NIC bridging the gap between HPC and real-time HEP GPU computing

TL;DR: The NaNet architecture and its performances are described, exhibiting two of its use cases: the GPU-based low-level trigger for the RICH detector in the NA62 experiment at CERN and the on-/off-shore data transport system for the KM3NeT-IT underwater neutrino telescope.
Proceedings ArticleDOI

Enabling technologies for GPU driven adaptive optics real-time control

TL;DR: PRANA (Prototype Real-time Architecture for the Next generation Ao) is a pathfinder for a reliable, scalable and energy efficient GPU-based AO real-time controller able to target the extremely large telescopes case.
Journal ArticleDOI

NaNet-10: A 10GbE network interface card for the GPU-based low-level trigger of the NA62 RICH detector

TL;DR: A GPU-based low level (L0) trigger is currently integrated in the experimental setup of the RICH detector of the NA62 experiment to assess the feasibility of building more refined physics-related trigger primitives and thus improve the trigger discriminating power.
References
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Journal ArticleDOI

APEnet+: a 3D Torus network optimized for GPU-based HPC Systems

TL;DR: The QUonG project is reported on the status of final rack deployment and on the R&D activities for 2012 that will focus on performance enhancement of the APEnet+ hardware through the adoption of new generation 28 nm FPGAs allowing the implementation of PCIe Gen3 host interface and the addition of new fault tolerance-oriented capabilities.
Journal ArticleDOI

ALICE HLT TPC Tracking of Pb-Pb Events on GPUs

TL;DR: In this article, the TPC online tracker implementation combines the principle of the cellular automaton and the Kalman filter for particle trajectories in the Time Projection Chamber (TPC).
Posted Content

GPU peer-to-peer techniques applied to a cluster interconnect

TL;DR: In this paper, the authors describe the architectural modifications required to implement peer-to-peer access to NVIDIA Fermi- and Kepler-class GPUs on an FPGA-based cluster interconnect.

KM3NeT:Technical Design Report for a Deep-SeaResearch Infrastructure in theMediterranean Sea Incorporating aVery Large Volume Neutrino Telescope

P. Bagley, +338 more

ALICE HLT TPC Tracking of Pb-Pb Events on

TL;DR: The online event reconstruction for the ALICE experiment at CERN requires processing capabilities to process central Pb-Pb collisions at a rate of more than 200 Hz, corresponding to an input data rate of about 25 GB/s.
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