Proceedings ArticleDOI
Novel CMOS ternary flip-flops using double pass-transistor logic
Guoqiang Hang,Xuanchang Zhou +1 more
- pp 5978-5981
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TLDR
In this paper, a novel CMOS D-type and modular algebra-based edge-triggered ternary flip-flops using double pass-transistor logic (DPL) are presented.Abstract:
Novel CMOS D-type and modular algebra-based edge-triggered ternary flip-flops using double pass-transistor logic(DPL), are presented. In the proposed circuit scheme, literal functions are also realized by using traditional MOS transistors without any modification of the thresholds. The DPL-based flip-flop has some favourable properties: perfectly symmetrical structure, full logic swing and the maximum possible noise margins, the less complex structure, and no static power consumption. The proposed D-type flip-flop consists of complementary inputs/outputs and is thus a dual rail ternary flip-flop. The modular algebra-based flip-flop can give triple-rail ternary complementary outputs. HSPICE simulations using 0.35µm CMOS technology and a 3V power supply demonstrate the effectiveness of the proposed design approach.read more
Citations
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Journal ArticleDOI
Benchmarking of DPL-based 8b × 8b novel wave-pipelined multiplier
TL;DR: In this paper, double pass-transistor logic (DPL) based 8b × 8b wave-pipelined pair-wise multiplier was evaluated on TSMC-0.18µm single-poly double-metal (SPDM) technology at 25°C temperature.
Journal ArticleDOI
DPL-based novel CMOS 1-Trit Ternary Full-Adder
TL;DR: A new high-speed, low-power, area-efficient 1-trit Ternary-Full-Adder (TFA) as a building block for wave-pipelined ternary-digital system design is presented, and Balanced input capacitance with structural symmetry makes Double Pass-transistor Logic (DPL) an ideal candidate for this.
Journal ArticleDOI
DPL-based novel time equalized CMOS ternary-to-binary converter
Aloke Kumar Saha,Dipankar Pal +1 more
TL;DR: Radix-3 (Ternary) logic has been receiving renewed attention as a feasible alternative to conventional Radix-2 system in processor-design and multi-valued logic-design due to computational-ease, sparsity, and robustness as discussed by the authors.
Journal ArticleDOI
A novel ternary JK flip-flop using the resonant tunneling diode literal circuit
Mi Lin,Ling-ling Sun +1 more
TL;DR: A literal circuit with a three-track-output structure is presented based on resonant tunneling diodes (RTDs) and can be transformed conveniently into a single- Track Output structure according to the definition and properties of the literal operation.
Journal ArticleDOI
Pair-Wise Urdhava-Tiryagbhyam (UT) Vedic Ternary multiplier
TL;DR: In this paper, a ternary multiplier based on Vedic Urdhava-Tiryagbhyam (UT) Sutra with Pair-Wise strategy and wave-pipelining is presented.
References
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Journal ArticleDOI
A 1.5-ns 32-b CMOS ALU in double pass-transistor logic
Suzuki Makoto,Norio Ohkubo,T. Shinbo,Toshiaki Yamanaka,Akihiro Shimizu,Katsuro Sasaki,Y. Nakagome +6 more
TL;DR: A carry propagation circuit technique called conditional carry selection (CCS) is shown to resolve the problem of series-connected pass transistors in the carry propagation path and the addition time of a 32-b ALU can be reduced by 30% from that of an ordinary CMOS ALU.
Journal ArticleDOI
Depletion/enhancement CMOS for a lower power family of three-valued logic circuits
A. Heung,H.T. Mouftah +1 more
TL;DR: A new family of ternary logic circuits that uses both depletion and enhancement types of complementary metal-oxide semiconductor (CMOS) transistors is presented.
Journal ArticleDOI
Design and application of pipelined dynamic CMOS ternary logic and simple ternary differential logic
Chung-Yu Wu,Huan-Shun Huang +1 more
TL;DR: The proposed dynamic ternary gates do not dissipate DC power and have full voltage swings, and the structure has the advantages of higher operating frequency, less latency, and lower device count as compared with the conventional binary parallel pipelined multiplier.
Journal ArticleDOI
General method in synthesis of pass-transistor circuits
TL;DR: The method is applied to generation of basic two-input and three-input logic gates in CPL, DPL and DVL, but it is general and can be expanded to synthesis of a random pass-transistor circuit.
Proceedings ArticleDOI
Design of quaternary logic gate using double pass-transistor logic with neuron MOS down literal circuit
TL;DR: The DPL improved the gate speed without increasing the input capacitance, and the quaternaryMIN (QMIN)/negated MIN (QNMIN) gate, andThe quaternaries MAX (QMAX)/negations MAX (NMAX) gate are designed using double pass-transistor logic (DPL) with neuron MOS (vMOS) threshold gates.
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