Proceedings ArticleDOI
On the computation of the ranges of detected delay fault sizes
A.K. Pramanick,Sudhakar M. Reddy +1 more
- pp 126-129
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TLDR
A method is proposed to determine all the possible ranges of detected fault sizes, thereby maximizing the fault coverage of a given test sequence, and methods are given to achieve such coverages wherever possible.Abstract:
Existing methodologies for determining gate delay fault coverages through the computation of detected fault sizes are shown to have certain deficiencies A method is proposed to determine all the possible ranges of detected fault sizes, thereby maximizing the fault coverage of a given test sequence The ultimate goal of ensuring that the coverage for a particular fault extends up to the actual circuit slack is explored, and methods are given to achieve such coverages wherever possible Results of experiments performed to evaluate the practical benefits of the proposed methods are reported >read more
Citations
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Proceedings ArticleDOI
"resistive shorts" within cmos gates
Hong Hao,Edward J. McCluskey +1 more
TL;DR: It is found that faults caused by transistor gate-to-source and gate- to-drain shorts can be dependent not only on inputs of gates containing the faults but also on other signals.
Proceedings ArticleDOI
On the design of path delay fault testable combinational circuits
A.K. Pramanick,Sudhakar M. Reddy +1 more
TL;DR: A theoretical framework for investigating the design for the path-delay-fault testability problem is provided and a design procedure is given for the synthesis of multioutput, multilevel combinational logic circuits in which all path delay faults are robustly detectable.
Proceedings ArticleDOI
On generating high quality tests for transition faults
TL;DR: Experimental results show that POTENT generates higher quality transition fault test sets than the conventional test generation method.
Proceedings ArticleDOI
Delay testing of digital circuits by output waveform analysis
P. Franco,Edward J. McCluskey +1 more
TL;DR: A new method for delay fault testing of digital circuits is presented, where instead of only latching the outputs at the sampling time, the output waveforms between samples are analyzed as well, and two classes of output waveform analysis are discussed.
Journal ArticleDOI
An efficient delay test generation system for combinational logic circuits
Eun Sei Park,M.R. Mercer +1 more
TL;DR: A novel timing analysis method for delay test generation which uses a conventional depth-first search technique and a novel functionality analysis technique is introduced which estimates the upper bound of the good circuit propagation delay of the longest sensitizable path passing through the fault site.
References
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Proceedings Article
Model for Delay Faults Based Upon Paths
TL;DR: A procedure is described which identifies paths which are tested for path faults by a set of patterns, independent of the delays of any individual gate of the network, which is a global delay fault model.
Journal ArticleDOI
On Delay Fault Testing in Logic Circuits
Chin Jen Lin,Sudhakar M. Reddy +1 more
TL;DR: Algorithms, based on a five-valued logic system, to accurately calculate the detection probability of path delay faults by random delay tests as well as to derive deterministic tests to detect pathdelay faults are proposed.
Proceedings ArticleDOI
On the detection of delay faults
A.K. Pramanick,Sudhakar M. Reddy +1 more
TL;DR: An algorithm was devised and implemented to automate the process of test generation, and results of experimentation with the ATPG, as well as with a random-pattern simulator, on four ISCAS-85 circuits were reported.
Journal ArticleDOI
An Experimental Delay Test Generator for LSI Logic
TL;DR: The program has successfully produced sets of delay tests for large logic networks and the average coverage achieved by these tests faDs within 95.8 percent to 99.9 percent of optimal.