Patent
One transistor dram cell structure and method for forming
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TLDR
In this article, the first source/drain region includes a Schottky diode junction with the body region, and the second source/drone region includes an n-p diod junction with body region.Abstract:
A one-transistor dynamic random access memory (DRAM) cell includes a transistor (10) which has a first source/drain region (26) a second source/drain region (24), a body region (36) between the first and second source/drain regions, and a gate (28) over the body region. The first source/drain region includes a Schottky diode junction with the body region and the second source/drain region includes an n-p diode junction with the body region.read more
Citations
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References
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Journal ArticleDOI
Memory design using one-transistor gain cell on SOI
Takashi Ohsawa,Katsuyuki Fujita,Tomoki Higashi,Yoshihisa Iwata,Takeshi Kajiyama,Yoshiaki Asao,Kazumasa Sunouchi +6 more
TL;DR: In this paper, a floating body transistor cell (FBC) has been used to achieve a 4F/sup 2/cell using self-aligned contact technologies and is proved to be scalable with respect to a cell signal.
Journal ArticleDOI
A capacitor-less 1T-DRAM cell
TL;DR: A simple true 1 transistor dynamic random access memory (DRAM) cell concept is proposed for the first time, using the body charging of partially-depleted SOI devices to store the logic "1" or "0" binary states.
Proceedings ArticleDOI
A SOI capacitor-less 1T-DRAM concept
TL;DR: In this article, a simple 1T DRAM cell concept is proposed for the first time, which exploits the body charging of PD SOI devices to store the information and allows the manufacture of low cost DRAMs and eDRAMs for 100 and sub 100 nm generations.
Patent
Semiconductor memory device and method of manufacturing the same
TL;DR: In this paper, a semiconductor memory device having MIS transistors to constitute memory cells (MC) is described, where each MIS transistor has a first data state in which the channel body is set at a first potential and a second data state at a second potential, and an auxiliary gate is provided separately from the main gate to control a potential of channel body by capacitive coupling.
Patent
Vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region
TL;DR: In this article, a 1T/FB dynamic random access memory (DRAM) cell is provided that includes a field effect transistor fabricated using a process compatible with a standard CMOS process.