Patent
Vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region
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TLDR
In this article, a 1T/FB dynamic random access memory (DRAM) cell is provided that includes a field effect transistor fabricated using a process compatible with a standard CMOS process.Abstract:
A one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell is provided that includes a field-effect transistor fabricated using a process compatible with a standard CMOS process. The field-effect transistor includes a source region and a drain region of a first conductivity type and a floating body region of a second conductivity type, opposite the first conductivity type, located between the source region and the drain region. A buried region of the first conductivity type is located under the source region, drain region and floating body region. The buried region helps to form a depletion region, which is located between the buried region and the source region, the drain region and the floating body region. The floating body region is thereby isolated by the depletion region. A bias voltage can be applied to the buried region, thereby controlling leakage currents in the 1T/FB DRAM cell.read more
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References
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Journal ArticleDOI
A capacitor-less 1T-DRAM cell
TL;DR: A simple true 1 transistor dynamic random access memory (DRAM) cell concept is proposed for the first time, using the body charging of partially-depleted SOI devices to store the logic "1" or "0" binary states.
Patent
Semiconductor integrated circuit device and process for manufacturing the same
Shuji Ikeda,Toshiaki Yamanaka,Kenichi Kikushima,Mitani Shinichiro,Kazushige Sato,Akira Fukami,Masaya Iida,Akihiro Shimizu +7 more
TL;DR: In this paper, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wires lines over the first conductance layer, which is formed by using resistance lowering means such as silicification.
Patent
Highly compact memory device with nonvolatile vertical transistor memory cell
TL;DR: In this paper, a highly compact nonvolatile solid state memory core is provided that stores and reproduces both digital and analog signals for multimedia applications, including vertical electrically erasable and programmable read only memories (EEPROM) cells having, for example, a stacked gate or a split channel configuration.
Patent
Memory cell that includes a vertical transistor and a trench capacitor
TL;DR: In this paper, a memory cell for a dynamic random access memory includes a pass transistor and a storage capacitor, where the transistor is a vertical transistor formed along an upper portion of a sidewall of a polysilicon-filled trench in a monocrystalline silicon body with the source and drain in the body and the source contact, gate and gate contact in the trench, with its gate dielectric being an oxide layer on the sidewall portion of the trench.
Patent
Static ram cell with trench pull-down transistors and buried-layer ground plate
TL;DR: In this paper, a (4T-2R) SRAM cell and method which achieves a much reduced cell area through the combined use of vertical trench pull-down n-channel transistors and a buried-layer ground plate is described.
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