Journal ArticleDOI
Parallel Decodable Multi-Level Unequal Burst Error Correcting Codes for Memories of Approximate Systems
Kazuteru Namba,Fabrizio Lombardi +1 more
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TLDR
The results of this manuscript confirm that the proposed multi-level burst error correcting UEP codes reduce the hardware overhead with no significant degradation in storage protection as potential storage application for approximate computing systems.Abstract:
Processing at the nanometric scales presents unique challenges that may require new computational paradigms such as approximate computing. In this paper a novel approach to memory protection using an unequal protection code (UEP) is proposed; this approach is in synergy with approximate (or inexact) computing. Multi-level burst error correcting UEP codes are analyzed. These codes improve over previously presented two-level burst error correcting UEP codes, because they utilize different conditions and criteria in the code partitions and decoder construction. An analysis by which multiple partitions can be selected to reduce the expected error magnitude, is provided. The area and power consumption of the parallel decoders closely depend on the desired code function. Simulation shows that the area and power consumption of the parallel error pattern generator are proportional to the partition length; the gate depth however is not strongly related to the partition length. The results of this manuscript confirm that the proposed multi-level burst error correcting UEP codes reduce the hardware overhead with no significant degradation in storage protection as potential storage application for approximate computing systems.read more
Citations
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Journal ArticleDOI
Soft Error Tolerant Count Min Sketches
TL;DR: The effect of soft errors on the Count Min Sketch is evaluated by injecting errors and a protection technique that does not require additional memory bits is presented and compared with the protection using a parity bit.
Journal ArticleDOI
Reduced Precision Redundancy for Reliable Processing of Data
TL;DR: A novel N-N Reduced Precision Redundancy scheme is proposed with a simple comparison-based approach and a probabilistic analysis is pursued to determine the conditions by which RPR data is provided as output; it is shown that its probability is very small.
Journal ArticleDOI
Extended Coset Decoding Scheme for Multi-bit Asymmetric Errors in Non-volatile Memories
TL;DR: This paper proposes an extended coset decoding scheme for NVMs that can be extended to other linear block codes and is rather suitable for scenarios with multi-bit asymmetric error features.
References
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Proceedings ArticleDOI
Approximate computing: An emerging paradigm for energy-efficient design
Jie Han,Michael Orshansky +1 more
TL;DR: This paper reviews recent progress in the area, including design of approximate arithmetic blocks, pertinent error and quality measures, and algorithm-level techniques for approximate computing.
Journal ArticleDOI
New Metrics for the Reliability of Approximate and Probabilistic Adders
TL;DR: New metrics are proposed for evaluating the reliability as well as the power efficiency of approximate and probabilistic adders and it is shown that the MED is an effective metric for measuring the implementation accuracy of a multiple-bit adder and that the NED is a nearly invariant metric independent of the size of an adder.
Proceedings ArticleDOI
IMPACT: imprecise adders for low-power approximate computing
TL;DR: This paper proposes logic complexity reduction as an alternative approach to take advantage of the relaxation of numerical accuracy, and demonstrates this concept by proposing various imprecise or approximate Full Adder cells with reduced complexity at the transistor level, and utilizing them to design approximate multi-bit adders.