Showing papers in "IEICE Electronics Express in 2017"
TL;DR: A novel technique, singular value decomposition approximation (SVDA) to reduce the usage of resources in 2D convolution in CNN is proposed and experimental results show that the proposed SVDA hardware implementation can achieve a reduction in resources.
Abstract: Convolutional neural network(CNN), a well-known machine learning algorithm, has been widely used in the field of computer vision for its amazing performance in image classification. With the rapid growth of applications based on CNN, various acceleration schemes have been proposed on FPGA, GPU and ASIC. In the implementation of these specific hardware accelerations, the most challenging part is the implementation of 2D convolution. To obtain a more efficient design of 2D convolution in CNN, this paper proposes a novel technique, singular value decomposition approximation (SVDA) to reduce the usage of resources. Experimental results show that the proposed SVDA hardware implementation can achieve a reduction in resources in the range of 14.46% to 37.8%, while the loss of classification accuracy is less than 1%.
34 citations
TL;DR: A novel, frequency selective surface (FSS) inspired, fully passive, chipless data encoding circuit capable of being operated as a radio frequency identification (RFID) tag is presented.
Abstract: A novel, frequency selective surface (FSS) inspired, fully passive, chipless data encoding circuit capable of being operated as a radio frequency identification (RFID) tag is presented. The tag is ...
30 citations
TL;DR: This paper presents a hardware Trojan classification method that performs a static analysis in gate-level netlist based on the controllability and observability characteristics extracted in a circuit that can achieve up to 100% true positive rate.
Abstract: This paper presents a hardware Trojan classification method that performs a static analysis in gate-level netlist. Based on the controllability and observability characteristics extracted in a circuit, the nets are clustered into two groups with the k-means method. Then inter-cluster distance is measured and taken as the major feature for Trojan identification. By combined with three other features in terms of circuit scale statistic number, a complementary representation of Trojan circuits is constructed. Finally, a support vector machine classifier is trained to distinguish the Trojan circuits from genuine circuits. Experimental results on Trust-HUB benchmarks demonstrate that our method can achieve up to 100% true positive rate.
26 citations
22 citations
20 citations
18 citations
TL;DR: A miniaturized frequency selective surface (FSS) composed of wire grid and tortuous pattern of cross-dipole element has been proposed to realize a first-order band-pass response.
Abstract: A miniaturized frequency selective surface (FSS) composed of wire grid and tortuous pattern of cross-dipole element has been proposed to realize a first-order band-pass response. Resonant frequency of the proposed FSS can be adjusted by changing tortuous factor of the cross-dipole element. Sharper one-side roll-off characteristic and better resonant frequency angular stability can be obtained by the proposed FSS with a larger tortuous factor. Also, by cascading the proposed FSS of different tortuous factors, a dualband frequency filter property can be obtained. The proposed FSS is analyzed by equivalent circuit method and full-wave simulations.
18 citations
TL;DR: The proposed method was verified by measurement of dielectric anisotropy of two LC mixtures, and error analysis has shown that the maximum error of the extracted permittivity was less than 1%.
Abstract: A method for accurate measurement of liquid crystal (LC) dielectric constant at lower terahertz region based on a metamaterial absorber, is proposed. In the proposed method, the permittivities are obtained by fitting the simulated spectral responses to the measurement results of a metamaterial (MM) absorber, in which LC layer acts as a substrate. The proposed method was verified by measurement of dielectric anisotropy of two LC mixtures, and error analysis has shown that the maximum error of the extracted permittivity was less than 1%.
18 citations
TL;DR: The problem that mechanical suitable materials with lower permittivity are not available in the classic bandwidth compensation technique has been solved and the proposed technique has equal performance in stabilizing the bandwidth of FSS radome under oblique incidence.
Abstract: In this paper, a feasible compensation technique has been proposed to improve the bandwidth angular stability of FSS radome. Stacked structure composed of different mechanical suitable materials has been adopted to construct the bandwidth compensation layer in the proposed technique. Hence, the problem that mechanical suitable materials with lower permittivity are not available in the classic bandwidth compensation technique has been solved. The validity of the proposed technique is verified by designing an FSS radome composed of modified second-order miniaturised FSS (MFSS) and bandwidth compensation layers. Simulation results show that the proposed technique has equal performance in stabilizing the bandwidth of FSS radome under oblique incidence with the classic one.
17 citations
17 citations
TL;DR: A single-end-access strain/temperature sensor configuration based on multimodal interference in a polymer optical fiber with an extremely high sensitivity and high strain and temperature sensitivities is developed.
Abstract: We develop a single-end-access strain/temperature sensor configuration based on multimodal interference in a polymer optical fiber (POF) with an extremely high sensitivity. The light Fresnel-reflected at the distal open end of the POF is exploited. We obtain high strain and temperature sensitivities of –122.2 pm/με and 10.1 nm/ ̊C, respectively, which are shown to be comparable to those in two-end-access configurations.
TL;DR: A polarization insensitive, compact, fully-passive bit encoding structure exhibiting 1 : 1 resonator-to-bit correspondence is presented.
Abstract: A polarization insensitive, compact, fully-passive bit encoding structure exhibiting 1 : 1 resonator-to-bit correspondence is presented. Inspired by frequency selective surface (FSS) based microwav ...
TL;DR: A novel, frequency selective surface (FSS) based, data encoding structure amenable to be used as a chipless RFID tag is proposed.
Abstract: A novel, frequency selective surface (FSS) based, data encoding structure amenable to be used as a chipless RFID tag is proposed. The data encoding structure is made up of finite repetitions of a u ...
TL;DR: A novel vehicle detection sensor design in which dual microwave Doppler radar transceiver modules were used to detect the movement of a parking vehicle and the parking space occupancy detection accuracy was higher than 98%.
Abstract: This paper described a novel vehicle detection sensor design in which dual microwave Doppler radar transceiver modules were used to detect the movement of a parking vehicle. A motion recognition algorithm was also presented to identify the vehicle behavior and generate the parking space occupancy status. Comparing with existing methods such as magnetometer and optical based detection, the proposed design simplified engineering integration from complex optical system design as well as achieved a high detection accuracy. Experimental results showed that the proposed dual microwave Doppler radar sensor detected the vehicle movement clearly and the parking space occupancy detection accuracy was higher than 98%.
TL;DR: A fully pipelined compression accelerator for the Lempel-Ziv (LZ) compression algorithm is presented, verified by using FPGA and fabricated using 65nm CMOS technology.
Abstract: Hardware accelerators are being considered as important architectural components in the context of datacenter customization to achieve high performance and low power. Compression has played an important role in computer systems by enhancing storage and communication efficiency in the charge of extra computational cost. In this letter, we present a fully pipelined compression accelerator for the Lempel-Ziv (LZ) compression algorithm. The compression accelerator is verified by using FPGA and fabricated using 65nm CMOS technology.
TL;DR: An efficient class-AB OTA with enhanced output current, slew rate, open loop gain, and gain bandwidth is presented, and measurement results of a 180 nm CMOS test chip prototype show slew rates, gain bandwidth, and openloop gain enhancement.
Abstract: An efficient class-AB OTA with enhanced output current, slew rate, open loop gain, and gain bandwidth is presented. The circuit is based on a class-AB input stage with adaptive biasing, and an output stage with dynamically biased cascode transistors. It can deliver output currents 100 times larger than the bias current with a total quiescent power dissipation of 72 μW. Measurement results of a 180 nm CMOS test chip prototype show slew rate, gain bandwidth, and open loop gain enhancement.
TL;DR: A phase shift pulse BOTDR (PSP-BOTDR) using probes composed of long and short pulses with phase shift keying modulation is proposed, and its performance is evaluated by experiment and simulation.
Abstract: We propose a phase shift pulse BOTDR (PSP-BOTDR) using probes composed of long and short pulses with phase shift keying modulation, and evaluate its performance by experiment and simulation. Modifying the previous probe configuration reduces signal leakage from the adjacent section to a negligible extent, and achieves truely a spatial resolution of 20 cm.
TL;DR: A novel radiation-hardened SRAM cell is presented by using the PMOS transistors stacked (each PMOS is split into two same sizes) and changing the inner topological structure on basis of the Quatro-10T, which exhibits larger static noise margin (SNM) as well as lower power consumption in 65nm COMS technology.
Abstract: This paper intends to present a novel radiation-hardened SRAM cell by using the PMOS transistors stacked (each PMOS is split into two same sizes) and changing the inner topological structure on basis of the Quatro-10T. Combined with layout-level optimization design, the 3-D TCAD mixed-mode simulation results show that the novel design has a great single event upset (SEU) immune. Simultaneously, it is found to be tolerant of partial single-event multiple-node upsets (SEMNUs) due to the charge sharing among off-PMOS transistors. In addition, compared with the Quatro-10T, our proposed structure exhibits larger static noise margin (SNM) as well as lower power consumption in 65nm COMS technology.
TL;DR: The results demonstrate that the proposed fast relocation algorithm can largely reduce the receiver relocation time, and shows the relocation can be realized during 1 second while the traditional receiver usually needs at least 6 seconds for the relocation after the signal blockage.
Abstract: In this paper, a fast relocation method is proposed, implemented and evaluated in a DSP/FPGA based GPS/SINS/CSAC deep integration hardware prototype. For the GPS receiver, when signal appears after the signal blockage or signal interference, the precise time information based on the reference of the CSAC and the position information from the SINS combined with the ephemeris can be used to calculate the frame counts and aid the realization of the fast relocation. A field test is conducted to verify and evaluate the performance of the algorithm. The results demonstrate that the proposed fast relocation algorithm can largely reduce the receiver relocation time. The result shows the relocation can be realized during 1 second while the traditional receiver usually needs at least 6 seconds for the relocation after the signal blockage.
TL;DR: Measurement results verify that the proposed enhancement techniques of bandwidth and efficiency are effective for DPA.
Abstract: This paper proposes a modified Doherty power amplifier (DPA) configuration for bandwidth and efficiency operations. To mitigate the efficiency degradation resulting from the incomplete load modulation network (LMN) and the knee voltage effect, the carrier transistor’s optimum load impedances based on related constant voltage standing wave ratio (VSWR) circle theory are introduced. Meanwhile, a innovative LMN with broadband matching technologies is adopted, which plays a guiding role on the bandwidth expansion from the theoretical point of view. In order to verify the practical feasibility of the design scheme, two 10W GaN HEMT transistors are used to design a broadband DPA. The measurement results show that the working bandwidth of the power amplifier is from 1.6GHz to 2.6GHz. The saturated output power of the whole frequency band is about 41.7–44 dBm and the drain efficiency (DE) is more than 50.8% at the input power of 33 dBm. In addition, the DE is 41.5–45% at 6-dB back-off power. Measurement results verify that the proposed enhancement techniques of bandwidth and efficiency are effective for DPA.
TL;DR: This work has succeeded in the first demonstration of a simple and accurate resonator-superconducting quantum interference device (SQUID) coupling for microwave SQUID multiplexers.
Abstract: We have succeeded in the first demonstration of a simple and accurate resonator-superconducting quantum interference device (SQUID) coupling for microwave SQUID multiplexers. A simple theory shows our direct coupling with adjustable fractional inductance in the SQUID loop can decrease the deviation of resonance frequencies from designed values in contrast to a conventional inductive coupling. Our direct coupling provides the individual coupling that can be optimized with keeping identical structure, shape, and dimension of the SQUID among all pixels on the same chip. It covers experimentally three or potentially more factors of a frequency band that is larger than that of cryogenic high electron mobility transistor amplifiers. The deviation of experimental fractional inductance from the designed one is less than −3/+10%.
TL;DR: A modified high gain setup up DC-DC quadratic boost converter is introduced that not only enhance the high voltage gain but also decrease the voltage stress across the semiconductor switches as well overall converter loses.
Abstract: High gain step up DC-DC boost converters are considered as an important part in different renewable energy sources (RES). In this paper a modified high gain setup up DC-DC quadratic boost converter is introduced. The proposed topology not only enhance the high voltage gain but also decrease the voltage stress across the semiconductor switches as well overall converter loses. To validate the proposed method efficacy, experiment performed in laboratory where 5 VDC are given as an input and at output we attained 62.5 volts with output power of 19.5 watts. The maximum efficiency of proposed converter at input power of 20W is 95.39% and at 3.7W it is 83.52%. Whereas, the conventional converter efficiency at the same input power is 93.89% and 82.96% respectively.
TL;DR: In E-ERA, reconfigurable computing arrays with approximate multipliers and dynamically adaptive accuracy controlling mechanism are implemented to achieve high energy efficiency and can achieve 304GOPS/W when processing RNNs for speech recognition.
Abstract: This paper proposes an Energy-Efficient Reconfigurable Architecture (E-ERA) for Recurrent Neural Networks (RNNs). In E-ERA, reconfigurable computing arrays with approximate multipliers and dynamically adaptive accuracy controlling mechanism are implemented to achieve high energy efficiency. The E-ERA prototype is implemented on TSMC 45 nm process. Experimental results show that, comparing with traditional designs, the power consumption of E-ERA is reduced by 28.6%∼52.3%, with only 5.3%∼9.2% loss in accuracy. Compared with state-of-the-art architectures, E-ERA outperforms up to 1.78X in power efficiency and can achieve 304GOPS/W when processing RNNs for speech recognition.
TL;DR: Simulation results show that the proposed DLLR scheme can significantly improve the error correcting performance of LDPC soft decoding in NAND flash memory.
Abstract: A dynamic log-likelihood ratio (DLLR) scheme based on expectation-maximization (EM) algorithm for the decoding of low-density parity-check (LDPC) codes in NAND flash memory is proposed. When LDPC soft decoding fails, the DLLR scheme employs the EM algorithm to estimate the parameters of the threshold voltage distribution of NAND flash memory, and then recalculates the LLR values for decoding. Simulation results show that the proposed scheme can significantly improve the error correcting performance of LDPC soft decoding in NAND flash memory.
TL;DR: This paper chipless RFID tag, capable of carrying 9-bit data, optimized for several flexible substrates, can be an ideal choice for deploying in various low-cost sensing applications.
Abstract: In this paper chipless RFID tag, capable of carrying 9-bit data is presented. The tag is optimized for several flexible substrates. With growing information and communication technology, sensor integration with data transmission has gained significant attention. Therefore, the tag with the same dimension is then optimized using paper substrate. For different values of permittivity, the relative humidity is observed. Hence, besides carrying information bits, the tag is capable of monitoring and sensing the humidity. The overall dimension of the tag comprising of 9 ring slot resonators is 7 mm. Due to its optimization on the paper substrate, the tag can be an ideal choice for deploying in various low-cost sensing applications
TL;DR: The numerical results show that the proposed algorithm can effectively improve the bit error rate and frame error rate performance compared with the conventional selection method, especially in high signal noise ratio (SNR) region.
Abstract: In the construction of polar code, the selection of frozen bits affects the error-correcting performance significantly. Several calculationbased algorithms have been proposed for general binary-input discrete memoryless channels (B-DMCs) like the additive white Gaussian noise (AWGN) channel. In this paper, a method for frozen bits selection based on Monte Carlo simulation and belief propagation (BP) decoding is proposed. The information bits are selected out one by one incrementally. The numerical results show that the proposed algorithm can effectively improve the bit error rate (BER) and frame error rate (FER) performance compared with the conventional selection method, especially in high signal noise ratio (SNR) region. Moreover, the algorithm can be used to construct polar codes with any rate through a complete iteration.