Parallel processing system having a broadcast, result, and instruction bus for transmitting, receiving and controlling the computation of data

TLDR: In this article, a parallel data broadcast architecture called "PDB" is adapted to a host computer system, which includes an interface and global memory which is connected to the host computer and to three common buses.

Abstract: A computer system utilizes a parallel data broadcast architecture, called "PDB" is adapted to be connected to a host computer system. In one digital embodiment, the PDB system includes an interface and global memory which is connected to the host computer system and to three common buses. The buses, in parallel, are, respectively, a data broadcast bus, an instruction bus and an output bus, each bus being connected to a plurality of computational units. Each computational unit includes an arithmetic processor, which preferably, in this embodiment, is a digital signal processor (a special-purpose integrated circuit microprocessor), a local memory and a local program memory. The computational units receive the input data simultaneously and in parallel; transform the data, depending on the parameters received from the instruction bus; and communicate their results, by multiplexing, to the output bus.