Proceedings ArticleDOI
PEAS-I: A hardware/software co-design system for ASIPs
Alauddin Al-Omary,Takeharu Nakata,Yoshimichi Honma,J. Sato,Nobuyuki Hikichi,Masaharu Imai +5 more
- pp 2-7
TLDR
A novel method that formulates the design of an optimal instruction set using an integer programming approach is described and a tool that enables the designer to predict the chip area and performance of the design before the detailed design is completed is discussed.Abstract:
The current implementation and experimental results of the PEAS-1 (practical environment for application specific integrated processor (ASIP) development - Version I) system are described. The PEAS-I system is a hardware/software co-design system for ASIP development. The input to the system is a set of application programs written in C language, an associated data set, and design constraints such as chip area and power consumption. The system generates an optimized CPU core design in the form of an HDL, as well as a set of application program development tools, such as a C compiler, assembler, and simulator. A novel method that formulates the design of an optimal instruction set using an integer programming approach is described. A tool that enables the designer to predict the chip area and performance of the design before the detailed design is completed is discussed. Application program development tools are generated in addition to the ASIP hardware design. >read more
Citations
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Proceedings ArticleDOI
Processor acceleration through automated instruction set customization
TL;DR: This paper presents the design of a system to automate the instruction set customization process, which contains a compiler subgraphmatching framework that identifies opportunities to exploit and generalize the hardware to support more computationgraphs.
Journal ArticleDOI
Automated custom instruction generation for domain-specific processor acceleration
TL;DR: The design of a system to automate the instruction set customization process is presented and generalization techniques are presented which enable the application-specific hardware to be more effectively used across a domain.
Journal ArticleDOI
Instruction set synthesis with efficient instruction encoding for configurable processors
TL;DR: This work builds a library of new instructions created with various encoding alternatives taking into account the data path architecture constraints, and chooses the best set of instructions while satisfying the instruction bitwidth constraint.
Proceedings ArticleDOI
Efficient instruction encoding for automatic instruction set design of configurable ASIPs
TL;DR: A novel instruction set synthesis technique that employs an efficient instruction encoding method to achieve maximal performance improvement and generates instruction sets that show improvements of up to 38% over the native instruction set for several realistic benchmark applications.
Proceedings ArticleDOI
Micro embedded monitoring for security in application specific instruction-set processors
TL;DR: This paper presents a methodology for monitoring security in Application Specific Instruction-set Processors (ASIPs), a generalized methodology for inline monitoring insecure operations in machine instructions at microinstruction level that embeds microinstructions into the critical machine instructions.
References
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BookDOI
High-Level VLSI Synthesis
Raul Camposano,Wayne Wolf +1 more
TL;DR: This chapter discusses architectural Synthesis for Medium and High Throughput Signal Processing with the new CATHEDRAL environment, and high-Level Synthesis in the THEDA System.
Proceedings ArticleDOI
Using Bottom-Up Design Techniques in the Synthesis of Digital Hardware from Abstract Behavioral Descriptions
TL;DR: This paper reports on a new method for using bottom-up design information in the synthesis of integrated circuits from abstract behavioral descriptions that draws on a newly developed procedural database to collect detailed information on the physical and logical properties of the primitives available for building the design.
Proceedings ArticleDOI
An integrated design environment for application specific integrated processor
TL;DR: A novel framework for ASIP (application specific integrated processor) development is proposed, which decides the instruction set and hardware architectures of ASIP, and synthesizes the CPU core design of the ASIP.
Book
Optimal VLSI Architectural Synthesis: Area, Performance and Testability
TL;DR: VLSI Design Cycle, Optimal Architectural Synthesis With Interfaces, and Oasic Synthesis Results: A Review and Background.