Proceedings ArticleDOI
Performance Optimization Using Exact Sensitization
Alexander Saldanha,Heather Harkness,Patrick C. McGeer,Robert K. Brayton,Alberto Sangiovanni-Vincentelli +4 more
- pp 425-429
Reads0
Chats0
TLDR
A new delay optimization procedure that optimizes only sensitizable paths greater than the desired delay t is described, and this method accounts for both functional and topological interactions in the circuit.Abstract:
A common approach to performance optimization of circuits focuses on re-synthesis to reduce the length of all paths greater than the desired delay t. We describe a new delay optimization procedure that optimizes only sensitizable paths greater than t. Unlike previous methods that use topological analysis only, this method accounts for both functional and topological interactions in the circuit. Comprehensive experimental results comparing the proposed technique to a state-of-the-art performance optimization procedure are presented for combinational and sequential logic circuits.read more
Citations
More filters
Proceedings ArticleDOI
A delay model for logic synthesis of continuously-sized networks
TL;DR: A new delay model for use in logic synthesis that allows to technology map using a library with continuous device sizing, satisfies certain electrical noise and power constraints, and is computationally simpler than a traditional model is presented.
Proceedings ArticleDOI
Optimizing sequential cycles through Shannon decomposition and retiming
TL;DR: This work proposes an efficient algorithm that simultaneously applies Shannon decomposition and retiming to optimize circuits with tight sequential cycles, and can be dramatic with only a modest increase in area.
Proceedings ArticleDOI
Logic Clause Analysis for Delay Optimization
TL;DR: This paper presents a novel method for topological delay optimization of combinational circuits which performs incremental network transformations, specifically substitutions of gate input or output signals by new gates.
Journal ArticleDOI
Low Cost Concurrent Error Masking Using Approximate Logic Circuits
Mihir Choudhury,Kartik Mohanram +1 more
TL;DR: Results indicate that concurrent error masking based on approximate logic circuits can mask 88% of targeted logical errors for 34% area overhead and 17% power overhead, and 100% timing errors on all timing paths within 20% of the critical path delay.
Proceedings ArticleDOI
Delay optimization using SOP balancing
TL;DR: A simple, fast, and very efficient synthesis algorithm to improve the delay after technology mapping that scales to large designs and is implemented in a publicly-available technology mapper.
References
More filters
Proceedings ArticleDOI
Sequential circuit design using synthesis and optimization
E.M. Sentovich,K.J. Singh,Cho W. Moon,Hamid Savoj,Robert K. Brayton,Alberto Sangiovanni-Vincentelli +5 more
TL;DR: SIS serves as both a framework within which various algorithms can be tested and compared and as a tool for automatic synthesis and optimization of sequential circuits.
Proceedings ArticleDOI
Timing optimization of combinational logic
TL;DR: An algorithm for speeding up combinational logic with minimal area increase is presented, using a static timing analyzer and a weighted min-cut algorithm to determine the subset of nodes to be resynthesized.
Proceedings ArticleDOI
Timing analysis and delay-fault test generation using path-recursive functions
Patrick C. McGeer,Alexander Saldanha,P.R. Stephan,Robert K. Brayton,Alberto Sangiovanni-Vincentelli +4 more
TL;DR: The authors introduce an efficient method for generating the functional forms of path analysis problems that holds promise for both static and dynamic hazard analysis and for test generation using all other delay-fault models, tau -irredundant fault models, and stuck-open fault models.
Journal ArticleDOI
Computing the initial states of retimed circuits
H.J. Touati,Robert K. Brayton +1 more
TL;DR: The authors present a simple linear time algorithm to compute a correct initial state for a retimed circuit that can be used whenever the initial state of the original circuit satisfies a simple condition.
Journal ArticleDOI
Critical path selection for performance optimization
TL;DR: It is shown that the path selection is different from path sensitization, and an input vector-oriented path selection algorithm is proposed, which may be infeasible for complex circuits with many primary inputs.