Patent
Power efficient stack of multicore microprocessors
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TLDR
In this article, a stack of microprocessor chips that are designed to work together in a multiprocessor system is discussed, and the hypervisor or operating system controls the utilization of individual chips of a stack.Abstract:
A computing system has a stack of microprocessor chips that are designed to work together in a multiprocessor system. The chips are interconnected with 3D through vias, or alternatively by compatible package carriers having the interconnections, while logically the chips in the stack are interconnected via specialized cache coherent interconnections. All of the chips in the stack use the same logical chip design, even though they can be easily personalized by setting specialized latches on the chips. One or more of the individual microprocessor chips utilized in the stack are implemented in a silicon process that is optimized for high performance while others are implemented in a silicon process that is optimized for power consumption i.e. for the best performance per Watt of electrical power consumed. The hypervisor or operating system controls the utilization of individual chips of a stack.read more
Citations
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References
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Proceedings ArticleDOI
PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor
Taeho Kgil,Shaun C. D'Souza,Ali G. Saidi,Nathan Binkert,Ronald G. Dreslinski,Trevor Mudge,Steven K. Reinhardt,Krisztian Flautner +7 more
TL;DR: It is shown how 3D stacking technology can be used to implement a simple, low-power, high-performance chip multiprocessor suitable for throughput processing and that a PicoServer performs comparably to a Pentium 4-like class machine while consuming only about 1/10 of the power.
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Memory module having interconnected and stacked integrated circuits
Vani Verma,Khushrav S. Chhor +1 more
TL;DR: A multi-chip memory module may be formed including two or more stacked integrated circuits mounted to a substrate or lead frame structure as mentioned in this paper, which can couple one or more of the integrated circuits to edge conductors in a memory card package configuration.
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Stackable memory card
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