Journal ArticleDOI
Range Unlimited Delay-Interleaving and -Recycling Clock Skew Compensation and Duty-Cycle Correction Circuit
Yi-Ming Wang,Shih-Nung Wei +1 more
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TLDR
Preliminary research results prove the feasibility of the proposed technique and show that the operating frequency ranges from 110 MHz to 1.75 GHz, with the corrected duty cycle varying from 51.2% to 48.9% based on 0.18-μm CMOS technology.Abstract:
A clock skew-compensation and duty-cycle correction circuit (CSADC) is used as the second-level clock distributing circuit to align a system global clock while maintaining a 50% duty cycle. A power-efficient, range-unlimited, and accuracy-enhanced CSADC, designed mainly with a new delay-interleaving and -recycling technique that mitigates operating frequency limitations while keeping overhead costs low, is proposed in this paper. Our preliminary research results prove the feasibility of the proposed technique and show that the operating frequency ranges from 110 MHz to 1.75 GHz, with the corrected duty cycle varying from 51.2% to 48.9% based on 0.18- $\mu $ m CMOS technology. Meanwhile, the lock-in time, static phase error, and power consumption are, respectively, 26 clock cycles, 4.2 ps, and 5.58 mW at 1.75 GHz.read more
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References
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A power-efficient wide-range phase-locked loop
Oscal T.-C. Chen,R.R.-B. Sheen +1 more
TL;DR: In this paper, a phase-locked loop for clock generation is presented, which consists of a phase/frequency detector, charge pump, loop filter, range-programmable voltage-controlled ring oscillator, and programmable divider.
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A 7 ps Jitter 0.053 mm $^{2}$ Fast Lock All-Digital DLL With a Wide Range and High Resolution DCC
TL;DR: A fast lock all-digital delay-locked loop (ADDLL) with a wide range and high resolution all- digital duty cycle corrector (ADDCC), which achieves low jitter, fast lock time, and accurate 50% duty cycle correction with a clock-synchronized delay (CSD) and time-to-digital converter (TDC) schemes.
Journal ArticleDOI
All-Digital Fast-Locked Synchronous Duty-Cycle Corrector
Shao-Ku Kao,Shen-Iuan Liu +1 more
TL;DR: An all-digital fast-locked synchronous duty-cycle corrector that corrects the duty cycle and synchronizes the input and output clocks in 10 clock cycles is presented.
Journal ArticleDOI
A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop
TL;DR: A half-delay-line circuit and an improved successive-approximation-register controller are developed on top of the coarse-fine architecture for fast lock-in, high duty-cycle-distortion tolerant, and low power.