Journal ArticleDOI
Rapid hardware prototyping on RPM-2
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The RPM-2 multiprocessor emulator uses this approach to achieve much greater flexibility and observability at less cost than typical hardware prototypes.Abstract:
Hardware emulation using FPGAs is an intermediate approach between software simulation and hardware prototyping. The RPM-2 multiprocessor emulator uses this approach to achieve much greater flexibility and observability at less cost than typical hardware prototypes.read more
Citations
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Proceedings ArticleDOI
So many states, so little time: verifying memory coherence in the Cray X1
TL;DR: A novel approach called "witness strings" that combines both formal and informal verification methods to expose design errors within the cache coherence protocol and its Verilog implementation is developed.
BEE3: Revitalizing Computer Architecture Research
TL;DR: The BEE3 is a production multi-FPGA system with up to 64 GB of DRAM and several I/O subsystems that can be used to enable faster, larger and higher fidelity computer architecture or other systems research.
Proceedings ArticleDOI
Remote and partial reconfiguration of FPGAs: tools and trends
TL;DR: The main contribution of the paper is the tool-set proposed to manipulate cores using partial reconfiguration in existing FPGA.
Journal ArticleDOI
MemorIES3: a programmable, real-time hardware emulation tool for multiprocessor server design
Ashwini K. Nanda,Kwok-Ken Mak,Krishnan Sugarvanam,Ramendra K. Sahoo,Vijayaraghavan Soundarararjan,T. Basil Smith +5 more
TL;DR: This paper presents the design of the Memory Instrumentation and Emulation System (MemorIES), a hardware-based emulation tool that can be used to aid memory system designers and observes that previous studies of SPLASH2 applications using scaled application sizes can result in optimistic miss rates relative to real sizes on real machines, providing potentially misleading data when used for design evaluation.
Proceedings ArticleDOI
DIMES: an iterative emulation platform for Multiprocessor-System-On-Chip designs
TL;DR: The preliminary results and experience of exploiting the iterative emulation technology in Cyclops emulation are reported and a multiprocessor-system-on-chip design of the IBM Cyclops architecture is implemented as a case study.
References
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Proceedings ArticleDOI
The SPLASH-2 programs: characterization and methodological considerations
TL;DR: This paper quantitatively characterize the SPLASH-2 programs in terms of fundamental properties and architectural interactions that are important to understand them well, including the computational load balance, communication to computation ratio and traffic needs, important working set sizes, and issues related to spatial locality.
Book
Parallel Computer Architecture: A Hardware/Software Approach
TL;DR: This book explains the forces behind this convergence of shared-memory, message-passing, data parallel, and data-driven computing architectures and provides comprehensive discussions of parallel programming for high performance and of workload-driven evaluation, based on understanding hardware-software interactions.
Journal ArticleDOI
A New Solution to Coherence Problems in Multicache Systems
TL;DR: A memory hierarchy has coherence problems as soon as one of its levels is split in several independent units which are not equally accessible from faster levels or processors.
Journal ArticleDOI
A survey of cache coherence schemes for multiprocessors
TL;DR: Schemes for cache coherence that exhibit various degrees of hardware complexity, ranging from protocols that maintain coherence in hardware, to software policies that prevent the existence of copies of shared, writable data, are surveyed.
Book
Synchronization, coherence, and event ordering in multiprocessors
TL;DR: In this paper, the cache coherence problem is examined, and solutions are described for both throughput-oriented and speedup-oriented multiprocessor systems, either at the user level or the operating-system level.