Run-time reconfigurable multi-precision floating point multiplier design for high speed, low-power applications
S Arish,Rajender Kumar Sharma +1 more
TLDR
This paper presents a run-time-reconfigurable floating point multiplier implemented on FPGA with custom floating point format for different applications and can have 6 modes of operations depending on the accuracy or application requirement.Abstract:
Floating point multiplication is one of the crucial operations in many application domains such as image processing, signal processing etc. But every application requires different working features. Some need high precision, some need low power consumption, low latency etc. But IEEE-754 format is not really flexible for these specifications and also design is complex. Optimal run-time reconfigurable hardware implementations may need the use of custom floating-point formats that do not necessarily follow IEEE specified sizes. In this paper, we present a run-time-reconfigurable floating point multiplier implemented on FPGA with custom floating point format for different applications. This floating point multiplier can have 6 modes of operations depending on the accuracy or application requirement. With the use of optimal design with custom IPs (Intellectual Properties), a better implementation is done by truncating the inputs before multiplication. And a combination of Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm (Vedic Mathematics) is used to implement unsigned binary multiplier. This further increases the efficiency of the multiplier.read more
Citations
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Proceedings ArticleDOI
High speed and area efficient single precision floating point arithmetic unit
Sangeeta Palekar,Nitin Narkhede +1 more
TL;DR: The intent of this design is to reduce the area and combinational path delay to enhance the speed of operation which is attained by parallelism in multiplier which is used for mantissa multiplication and performance is compared with latest research papers regarding delay.
Proceedings ArticleDOI
32-Bit RISC processor with floating point unit for DSP applications
Sangeeta Palekar,Nitin Narkhede +1 more
TL;DR: A high speed MIPS based 32 bit RISC processor with single precision floating point unit for DSP applications is proposed and results indicates that the proposed design is optimized in speed as well as in area.
Journal ArticleDOI
Design and Analysis of Multimode Single Precision Floating Point Arithmetic Unit Using Verilog
Sachin saraswat,Sunita Malik +1 more
TL;DR: The efficient multimode floating point arithmetic unit forEEE 754 floating point number system is designed and analysed, which gives a better implementation in terms of area of hardware and the number of LUTs used in FPGA is reduced.
Journal Article
An Exhaustive Research Survey on Vedic ALU Design
TL;DR: This paper concentrates on the related work on design of Vedic ALU, till date from 46 different IEEE papers and provides some common problem statements and solutions that can be used to design the bestALU, which is not done till date.
References
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Journal Article
Design of a High Speed Multiplier (Ancient Vedic Mathematics Approach)
TL;DR: In this paper, an area efficient multiplier architecture is presented based on Ancient algorithms of the Vedas, propounded in the Vedic Mathematics scripture of Sri Bharati Krishna Tirthaji Maharaja.
FPGA Implementation of Low-Area Floating Point Multiplier Using Vedic Mathematics
R. Sai Siva Teja,A. Madhusudhan +1 more
TL;DR: An efficient implementation of an IEEE 754 single precision floating point multiplier using vedic mathematics so that the area and power constraints of thefloating point multiplier can be reduced efficiently.
Proceedings ArticleDOI
A flexible multiplier for media processing
TL;DR: The results show that all the functionalities provided by the set of the other considered devices can be performed by the proposed design with a minor area overhead penalty and still competitive performance; thus the proposed multiplier represents a good candidate for usage in area-limited designs.
Proceedings ArticleDOI
Hardware implementation of variable precision multiplication on FPGA
TL;DR: A hardwired algorithm for computing the variable precision multiplication is presented, based on the use of a parallel multiplier of size m to compute the multiplication of two numbers of n×m bits.
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