Proceedings ArticleDOI
SATSim: a superscalar architecture trace simulator using interactive animation
Mark Wolff,Linda M. Wills +1 more
- pp 6
TLDR
An interactive animation tool, SATSim, which conveys superscalar architecture concepts, which allows students to interactively change hardware configuration parameters and to observe their effects visually in a more accessible manner than is currently possible with existing simulators or with traditional static media.Abstract:
This paper describes an interactive animation tool, SATSim, which conveys superscalar architecture concepts. It has been used in an advanced undergraduate computer architecture course to visualize the complicated behavioral patterns of superscalar architectures, such as out-of-order execution, in-order commitment, and the impact of branch mispredictions and cache misses. SATSim allows students to interactively change hardware configuration parameters and to observe their effects visually in a more accessible manner than is currently possible with existing simulators or with traditional static media.read more
Citations
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Journal ArticleDOI
Applying a constructivist and collaborative methodological approach in engineering education
TL;DR: A methodological educational proposal based on constructivism and collaborative learning theories is described, which has been successfully applied to a subject entitled ''Computer Architecture and Engineering'' in a Computer Science degree in the University of La Laguna in Spain.
Journal ArticleDOI
Use of Constructivism and Collaborative Teaching in an ILP Processors Course
TL;DR: This methodology has been applied in a computer architecture course that uses the Moodle platform as a framework for collaboration between students and teachers and goes one step beyond by using SIMDE with an educational methodology based on constructivism and collaborative learning.
Journal ArticleDOI
Integrating formal verification into an advanced computer architecture course
TL;DR: This paper presents a sequence of three projects on design and formal verification of pipelined and superscalar processors: a single-issue, five-stage DLX, an extension of the DLX with exceptions and branch prediction, and a dual-issue supers Calar DLX.
Proceedings ArticleDOI
A survey of web resources for teaching computer architecture
TL;DR: It is concluded that the computer-architecture community faces challenges both in the content of Web-based materials (accurate and appropriate information) and the process (making information known and available to academic community).
Proceedings ArticleDOI
The Potential of Virtual Reality for Computer Science Education -Engaging Students through Immersive Visualizations
TL;DR: In this article, the authors investigated the differences between subjective variables in a web application and a VR application for learning sorting algorithms and found that learners experience higher presence, absorption, flow, psychological immersion and positive emotions in a virtual reality setting compared to a desktop setting.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
The SimpleScalar tool set, version 2.0
Doug Burger,Todd Austin +1 more
TL;DR: This document describes release 2.0 of the SimpleScalar tool set, a suite of free, publicly available simulation tools that offer both detailed and high-performance simulation of modern microprocessors.
Journal ArticleDOI
The Alpha 21264 microprocessor
TL;DR: A unique combination of high clock speeds and advanced microarchitectural techniques, including many forms of out-of-order and speculative execution, provide exceptional core computational performance in the 21264.
Journal ArticleDOI
The Mips R10000 superscalar microprocessor
TL;DR: The Mips R10000 is a dynamic, superscalar microprocessor that implements the 64-bit Mips 4 instruction set architecture that fetches and decodes four instructions per cycle and dynamically issues them to five fully-pipelined, low-latency execution units.