IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 5, NO. 2, JUNE 1997 175
Scheduling Tests for VLSI Systems
Under Power Constraints
Richard M. Chou, Kewal K. Saluja, Fellow, IEEE,
and Vishwani D. Agrawal, Fellow, IEEE
Abstract—This paper considers the problem of testing VLSI
integrated circuits in minimum time without exceeding their
power ratings during test. We use a resource graph formu-
lation for the test problem. The solution requires finding a
power-constrained schedule of tests. Two formulations of this
problem are given as follows: 1) scheduling equal length tests
with power constraints and 2) scheduling unequal length tests
with power constraints. Optimum solutions are obtained for both
formulations. Algorithms consist of four basic steps. First, a
test compatibility graph is constructed from the resource graph.
Second, the test compatibility graph is used to identify a complete
set of time compatible tests with power dissipation information
associated with each test. Third, from the set of compatible
tests, lists of power compatible tests are extracted. And finally,
minimum cover table approach is used to find an optimum
schedule of power compatible tests.
Index Terms— Built-in self-test (BIST), low-power testing,
power-constrained scheduling, test scheduling, VLSI testing.
I. INTRODUCTION
D
URING the testing of a complex integrated circuit (IC),
digital board, or system, not all tests may be applied at
the same time due to resource conflicts. For example, in a
given system, suppose subsystem 1 and subsystem 2 share the
same inputs, but the test designed for subsystem 1 does not test
subsystem 2, and vice versa. Hence, the test for subsystem 2
must be applied at a different time than the test for subsystem
1. The same is true if subsystem 1 and subsystem 2 share
outputs, and the test results cannot be observed simultaneously.
In general, selected subsets of a complete test set of a system
may be applied simultaneously to test different functional
blocks provided there is no conflict for resources [1], [5], [9],
[12], [13], [18]. The tests that can be applied concurrently are
said to be time compatible or compatible [14]. Each application
of time compatible tests is called a test session, and the time
required for a test session is often referred to as test length
[5], [13]. In a complete test set, there may be many different
subsets of time compatible tests, and these subsets may or may
not be disjoint. Therefore, the tests must be scheduled in such
a way that suitable time compatible subsets completely test
the system while minimizing the total test time. This problem
Manuscript received June 28, 1994; revised October 25, 1995 and July 31,
1996. This work was supported in part by the National Science Foundation
under Grant MIP-9111886 and by a grant from the AT&T Foundation.
R. M. Chou and K. K. Saluja are with the Department of Electrical and
Computer Engineering, The University of Wisconsin, Madison, WI 53706
USA.
V. D. Agrawal is with Bell Labs, Lucent Technologies, Murray Hill, NJ
07974 USA.
Publisher Item Identifier S 1063-8210(97)01950-1.
was originally defined by Kime and Saluja [13] and has since
been studied by several researchers [1], [5], [9], [12], [18].
The basic approach in test scheduling is to find all time com-
patible test sessions and determine their ordered sequence to
minimize the total test length. The definition of the time com-
patibility of tests in all previous work [1], [5], [9], [12]–[14],
[18] considers only resource conflicts. However, as the device
technologies such as multichip modules (MCM’s) become
available, and larger and denser memory IC’s are called for by
the high-performance digital systems, the power consumption
becomes a critical factor and can no longer be ignored [6],
[23], either in normal operation of the system or under testing
environment. Absence of resource conflict for a pair of tests
does not mean that these two tests can be applied concurrently
to parts of a system, because the total power consumption
must not exceed the maximum power allowance in order to
guarantee proper operating conditions during test.
Consider the modern high-performance memory systems,
for example. Memories are organized into blocks of many
fixed sizes. Under normal system operation, exactly one block
is activated per memory access while other blocks are in
the power-down mode to minimize the power consumption.
Under testing environment, however, in order to test the
memory system in the shortest possible time, it is desirable to
concurrently activate as many blocks as possible provided that
the power consumption limit of the system is not exceeded.
Another example is the testing of MCM’s. An attractive
approach for testing MCM’s is to use built-in self-test (BIST)
blocks executing in parallel [11], [21], [23]. Under normal
operation, blocks are not simultaneously activated and hence,
the inactive blocks do not contribute to power dissipation.
However, a concurrent execution of BIST in many blocks
will result in high power dissipation which might exceed the
maximum power dissipation limit. To ensure the reliability
of the system, execution of the self-test blocks must be
scheduled in such a way that the maximum power dissipation
limit is not exceeded at all times during test. Therefore, the
power consumption constraint must be a consideration in the
scheduling of tests.
The power dissipation in a system is not only technology
dependent, it is also a function of clock frequencies among
other factors [6]. For example, in a synchronous CMOS sys-
tem, power dissipation is a function of the transistor switching
activity which occurs on the system clock edges. The faster
the clock frequency is, the more the switching activity over a
fixed period of time, and hence higher the power dissipation.
1063–8210/97$10.00 1997 IEEE
176 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 5, NO. 2, JUNE 1997
Fig. 1. Resource graph of an example system.
There are several ways in which the power consumption
requirements can be satisfied under testing environment. First,
clock(s) can be slowed down to reduce the average dynamic
power dissipation. However, in order to minimize the total test
time, it is desirable to test the system at the highest possible
frequency, which renders this method ineffective. Second, the
tests can be executed in sequential order such that no two
tests are overlapped in time. This method makes the test
scheduling problem trivial by excluding the possibilities of
exploring parallelism in applying the tests. Again, this method
defeats the purpose of minimizing the total test time. These
methods are two extremes in the attempt to reduce the power
dissipation during the test application at the expense of the
total test time. With the clock running at the highest possible
frequency, instead of maximizing test parallelism, a better way
of scheduling the tests would be to minimize the total test time
while satisfying the power constraints. Such considerations
have motivated the research discussed in this paper. Note that
the method developed in this paper is not only limited to
memory testing or BIST environment. It is also applicable
to other scenario as well. We formulate the problem with
power constraints added to the test scheduling consideration
and provide algorithmic solutions.
II. B
ACKGROUND AND PRELIMINARIES
A digital system can be viewed as a collection of intercon-
nected blocks, each consisting of combinational components
and storage registers. A test model for such a system consists
of combinational blocks
and register blocks , which are
jointly called resources, for a test
. The test problem can be
modeled as a bipartite resource graph, hereafter referred to as
a resource graph. As shown in Fig. 1, such a graph has been
used before [5], [13]. Here, the each test
is a sequence of
test vectors that can thoroughly test the block
. In Fig. 1,
the nodes at the top together form a complete set of tests, and
the bottom nodes depict the resource set. An edge connecting
a top node and a bottom node pairs a test with one of the
resources that the test requires.
The resource graph completely describes the covering rela-
tionship of the tests and the circuit blocks. In addition, it also
contains the information about resource conflicts. For example,
in Fig. 1, tests
and both use resource . This means
and cannot be executed at the same time. In other words,
these two tests are incompatible in time. Only the tests without
a resource conflict can be executed concurrently and hence are
compatible in time.
Fig. 2. Test compatibility graph (TCG) of the example system.
From the resource graph, it is possible to obtain the set of
all time compatible tests by deriving a test compatibility graph
(TCG) [5], [13] as shown in Fig. 2. The nodes in the TCG form
the complete test set. The edges between the nodes depict the
time compatibility of the connecting nodes. For example, in
Fig. 2 tests
, , and can be executed concurrently because
they are time compatible with each other.
With the TCG based on resource constraints, the test sched-
uling can be performed by first, finding the cliques [10], which
are the maximal complete subgraphs of a graph, in the TCG,
and then choosing a subset of the cliques according to a
cost function as the solution. All nodes in the same clique
can be executed concurrently since they are time compatible.
Thus, the scheduling problem reduces to that of finding a
minimum set of cliques such that all tests are covered. This
will give the optimal solution in terms of test time [5], [13].
Alternatively, this problem can also be formulated as a graph
coloring problem [5].
When power consumption is also considered in the schedul-
ing of tests, the clique solution is not sufficient. The nodes, or
equivalently the tests, in the same clique are time compatible
only with respect to the resource constraints. They may not
be compatible from the power consumption point of view
as executing all tests in the same clique might exceed the
maximum power limit imposed by the technology. In such
a case, they must not be scheduled in the same test session.
For example, consider the clique G1
in Fig. 2.
Assume that
requires two units of power, requires
one unit of power,
requires two units of power, and the
CHOU et al.: SCHEDULING TESTS FOR VLSI SYSTEMS 177
Fig. 3. Power dissipation as a function of time.
maximum power consumption rating of the device is four
units. From the resource conflict point of view, all three tests
may be executed at the same time. However, executing all
three tests concurrently requires five units of power, which
exceeds the maximum power limit. Obviously, these three tests
must not be scheduled for concurrent execution. This fact and
informal statements of results appear in a preliminary version
of this paper [4].
III. P
ROBLEM FORMULATION
Throughout this paper, the term test length will be used
as a measure of the real time required to perform the test.
Therefore, the terms test length and test time are used in-
terchangeably. Assume
, which consists of tests
, forms a complete set of tests (hereafter, also
called “test”), for the device under test. Each test
consists
of a sequence of test vectors to be applied to the device. A
test session
is a subset of such that all tests in can be
applied concurrently.
Notation:
test ;
test length of ;
max power dissipated when test alone is applied
to the device;
test session ;
time required for all test vectors in to be com-
pleted = Maximum
;
maximum power dissipation allowance of the device.
The power dissipation considered in this work includes both
the static and the dynamic power dissipations. Clearly, power
dissipation in a circuit or subcircuit is a function of time.
Normally, power dissipation at any given time in a circuit
depends on the circuit activity. In the case of a CMOS circuit,
it is a function of the switching activity for each input applied
to the circuit. In testing environment, the power dissipation
varies as each test vector is applied to the circuit.
The instantaneous power,
, is the power dissipation at
any time instant
, i.e., where and
are the instantaneous voltage and current in the circuit.
Both voltage and current are functions of time. However, in
general, the voltage supplied to the circuit does not vary, i.e.,
. Therefore, the current waveform will determine
the variation of power dissipation. This power dissipation as
a function of time may be obtained either from simulation
or from a direct measurement carried out on the hardware
components. An example of power dissipation waveforms, or
equivalently the current waveforms, for a short period of time
for tests
and are shown in Fig. 3 [3], [8], [22].
To simplify the analysis, the definition of the power dissi-
pation,
, for a test , which consists of a sequence of
test vectors applied over time, is assigned a fixed value for
the test
. Let and be the instantaneous power
dissipation of two compatible tests
and , respectively,
and
and be the corresponding maximum power
178 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 5, NO. 2, JUNE 1997
dissipation as shown in Fig. 3. Ideally, if , which
is the sum of the instantaneous powers of tests
and , does
not exceed the maximum power dissipation limit,
, then
and can be scheduled in the same test session. However,
in reality the instantaneous power for each test vector is hard
to obtain since it depends, e.g., in a CMOS circuit, on the
number of zero-to-one and one-to-zero transitions, which in
turn could be dependent on the order of execution of test
vectors. Consequently, different test schedules will result in
different instantaneous power dissipation profiles for the same
test. To simplify the analysis, we assign a fixed value
to
all test vectors in
such that at any time instant when the test
is in progress the power dissipation is no more than .
There are two ways
can be assigned. First, could
have been defined as the average power dissipation over all
test vectors in
. This definition might be overly optimistic in
the analysis of power dissipation when many test vectors are
applied simultaneously since the average value cannot reflect
the instantaneous power dissipation of each test vector. Hence,
it might lead to an undesirable test schedule which exceeds
the power dissipation allowance of the device at some time
instants.
Second,
can be defined as the maximum power
dissipation over all test vectors in
. This is the upper bound
power dissipation in
. This definition is pessimistic since
it disallows two tests
and whose peak powers occur
at different time instants from being scheduled in the same
test session as shown in Fig. 3. However, the test schedule
obtained with this definition guarantees the maximum power
dissipation allowance of the device to be observed at all time
instants. In the test environment, the difference between the
average and the maximum power dissipation for each test
is often small since the objective is to maximize the circuit
activity so that the circuit can be thoroughly tested in the
shortest possible time. Therefore, it is reasonable to define
to be the maximum power dissipation over all test
vectors in
. Hence, in the subsequent analysis, is
assumed to be the maximum power dissipation of test
. Note
that the statement of the problem and the constraints given
below are independent of the method of assigning values to
for a test .
With this definition of
, the power dissipation
for a test session can be defined as follows:
Therefore, the power constraint in test scheduling can be
defined as follows:
(3.1)
This inequality assures that the total power dissipation due
to simultaneous application of all test vectors in test session
does not exceed the total device power allowance
provided that for all .
1) Test Scheduling Problem: Minimize
under the power constraint (3.1) such that
every test
is executed at least once.
Fig. 4. TCG for power-constrained and equal test length scheduling.
The optimum solution to this test scheduling problem min-
imizes the total test length such that the device is completely
tested under power constraints. Tests can be divided into two
categories: 1) tests with equal length and 2) tests with unequal
lengths [5], [13]. With test length and the power dissipation
as the two variables to be simultaneously considered in min-
imization, four cases exist. From the simplest to the most
general, these cases are: 1) equal power dissipation, equal test
length, 2) unequal power dissipation, equal test length, 3) equal
power dissipation, unequal test length, and 4) unequal power
dissipation, unequal test length. In the equal test length cases,
the test length for each test is assumed to be identical, i.e.,
. Since we use the formulation in
which the total power consumed during concurrent execution
of tests is equal to the sum of powers consumed by individual
tests, the solutions to the above four cases can be considered
by grouping cases 1 and 2 together, and by grouping cases 3
and 4 together. This grouping forms two general classes: a) the
scheduling of equal length tests with power constraints and b)
the scheduling of unequal length tests with power constraints.
We now discuss solutions to these two problems. We must
point out that case a) is a special case of b), in which all test
lengths are set to the same constant
. Therefore, the solution
to case a is simpler to construct. An understanding of this
simpler scheduling approach will help the reader understand
the more complex algorithm presented in Section V.
IV. S
CHEDULING EQUAL LENGTH
TESTS WITH POWER CONSTRAINTS
For the example system whose resource graph is shown
in Fig. 1, we construct the corresponding TCG. The power-
constrained TCG is shown in Fig. 4. In this TCG, which is
topologically similar to Fig. 2, an ordered pair
is associated with each node . The first element is
the power requirement for executing the test
as defined
in the previous section, and the second element
is
the corresponding test length.
, the maximum power
consumption allowed by technology, is assumed to be four
units in this example.
CHOU et al.: SCHEDULING TESTS FOR VLSI SYSTEMS 179
Since all test lengths are equal (unequal test length are
considered in the next section), the objective is to find a power-
constrained test schedule that covers every test in at least one
test session such that the total time required for testing is
minimum. The solution is obtained in two steps: 1) identify
the solution space, and 2) search the solution space for an
optimum solution. To identify the solution space, we require
the following definitions.
Definition 1: A power compatible set (PCS) is a set of
tests that can be executed concurrently, i.e., they are time
compatible and still satisfy the power constraints given by
relation (3.1). The execution of the tests in the PCS is
equivalent to a test session as defined before.
In Fig. 4,
, , , , and are
the power compatible sets. Note that the definition of the
power compatible set does not guarantee that the sets are
disjoint. Overlaps are possible. In addition, one set can also
be completely contained in another set. For example,
is completely contained in . The time compatibility
requirement of tests in a PCS implies that the PCS’s must be
obtained from the cliques of the TCG. Each PCS represents a
test session to be considered in test scheduling. The scheduling
algorithm just selects the test sessions in an optimal way
such that the total execution time is minimum. Therefore,
the solution space for the scheduling algorithm is spanned
by all test sessions, or equivalently, all PCS’s extracted from
all cliques of the TCG. However, if all PCS’s so generated
are considered by the scheduling algorithm, it is equivalent to
an exhaustive search. Fortunately, it is possible to deal with a
smaller set of the PCS’s which still covers the solution space.
Definition 2: A maximum PCS is a PCS to which no
compatible test can be added without exceeding the maximum
power consumption limit. Thus, no maximum PCS can be
completely covered by any other PCS.
In the TCG of Fig. 4, the PCS’s generated from clique
are , , , , ,
and
, when the maximum allowable power is 4. However,
the maximum PCS’s are
, , and .
The set of maximum PCS’s (test sessions) generated from
all cliques of the TCG forms the minimum solution space
for the test scheduling problem under power constraints. If
one of the maximum PCS’s is selected for inclusion in the
final schedule, then all subsets of that maximum PCS are
automatically covered and, hence, the completeness of the
solution is justified. Next, in the search step, we find a set
with the smallest number of the maximum PCS’s that covers
all tests.
Note that in this case, all tests have the same length.
Consequently, the execution time of any test session is a
constant. Furthermore, each maximum PCS in the solution
space can be conceptually viewed as a prime implicant of a
logic function. Thus, any covering table minimization tech-
nique, as is normally used to minimize the number of prime
implicants of a logic function [2], [7], [16], will minimize the
number of maximum PCS’s required, and hence, minimize
the number of test sessions. Since each test session executes
in constant time, the total test time is also minimized. In
forming the maximum PCS’s from the cliques of TCG, power
Fig. 5. Power-constrained equal length test scheduling algorithm.
constraints are considered. It is not necessary to distinguish the
cases of equal and unequal power consumption by each block
since the equal power consumption case is just a special case
of the unequal consumption case. Hence, both cases can be
solved using the same scheduling algorithm. The scheduling
algorithm that provides an optimal solution is shown in Fig. 5.
For the example of Fig. 4, the steps of the scheduling
algorithm of Fig. 5 are as follows.
1) The TCG is given in Fig. 4.
2) All possible cliques of the TCG are
3) All possible maximum PCS’s ( ) are
obtained from G1
obtained from G2
obtained from G3
obtained from G4
obtained from G5
is not a maximum PCS since it is contained in
, and hence, it is excluded from the set of
maximum PCS’s.
4) Use of the covering table minimization procedure is
shown in Table I. In this table, each “x” indicates the
cover of a test by a maximum PCS. The covering
table minimization procedure results into the following
optimum schedule:
Test session length required
Test session length required
Test session length required
Total test length required
It can be easily verified that the solution obtained is indeed
an optimal schedule.
