Patent
Semiconductor integrated circuit device having hierarchical power source arrangement
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TLDR
In this paper, a variable impedance power supply line and variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period.Abstract:Â
A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in accordance with a logic level of an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.read more
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References
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Patent
Semiconductor integrated circuit device having power reduction mechanism
TL;DR: In this paper, the authors describe a logic gate with at least two MOS transistors connected to a first potential point and a second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the gate.
Journal ArticleDOI
Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's
TL;DR: In this paper, a switched-source-impedance (SSI) CMOS circuit is proposed as a means of reducing the exponential increase of sub-threshold current with threshold-voltage scaling.
Proceedings ArticleDOI
1V high-speed digital circuit technology with 0.5/spl mu/m multi-threshold CMOS
TL;DR: A 1-V high-speed and low-power digital circuit technology with 0.5/spl mu/m multi-threshold CMOS (MT-CMOS) is proposed, which applies both low-th threshold voltage and high-th thresholds voltage MOSFETs in one LSI.
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TL;DR: In this article, the authors proposed to scale down a capacitance measuring device while obtaining the precise value of trench capacitance by mounting first-third transistors turned ON under a first state and turned OFF under a second state.
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TL;DR: In this paper, a power up pulse generator circuit was proposed to generate a pulse of a predetermined duration in spite of a slow rate of change of applied power supply voltage and an input signal.