Sequential test pattern generation using clock-control design for testability structures

TLDR: In this article, a design for testability (DFT) structure is used to provide partitioning of a master clock into multiple clock signals each associated with a corresponding one of the levels of self-loops, so as to permit breaking of the feedback loops other than the selfloops.

Abstract: Techniques for testing a sequential circuit comprising a plurality of flip-flops or other types of registers. The circuit is first configured such that substantially all feedback loops associated with the registers, other than one or more self-loops each associated with a corresponding one of the registers, are broken. Test patterns are then generated for application to the circuit. The test patterns are applied to the circuit in conjunction with partitioned clock signals each of which is associated with a corresponding level of the circuit containing at least one of the self-loops. In an illustrative embodiment, a design for testability (DFT) structure is used to provide partitioning of a master clock into multiple clock signals each associated with a corresponding one of the levels of self-loops, so as to permit breaking of the feedback loops other than the self-loops. The registers of the circuit may be arranged in the particular levels by assigning a first one of the levels to each register which is fed only by primary inputs (PIs) of the circuit, and then assigning to level i+1 every register that is fed by other registers whose maximum level is i, where i=1, 2, . . . d, and d is the sequential depth of the circuit. In addition, each of the levels of registers may have multiple groups of registers associated therewith, with each of the groups being subject to clocking by one of the partitioned clock signals through the operation of group selection circuitry.